Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode having a two-sided staircase shape above the substrate, a blocking layer on the gate electrode, a plurality of discrete charge trapping layers each extending laterally on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of discrete channel layers each extending laterally on the tunneling layer. The plurality of charge trapping layers are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode, respectively. The plurality of channel layers are disposed corresponding to the stairs of the two-sided staircase shape, respectively.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate, an alternating layer stack on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes (i) an alternating dielectric stack having a plurality of dielectric layer pairs enclosed laterally by at least the barrier structure, and (ii) an alternating conductor/dielectric stack having a plurality of conductor/dielectric layer pairs. The 3D memory device also includes a channel structure and a source structure each extending vertically through the alternating conductor/dielectric stack, and a contact structure extending vertically through the alternating dielectric stack. The source structure includes at least one staggered portion along a respective sidewall.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a substrate and a stack structure in an insulating structure on the substrate. The stack structure includes alternating a plurality of conductor layers and a plurality of insulating layers. The 3D memory device further includes a source structure extending vertically through the alternating stack structure. The source structure includes at least one staggered portion along a respective sidewall. The 3D memory device further includes a channel structure and a support pillar each extending vertically through the alternating stack structure and a plurality of contact structures extending vertically through the insulating structure.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a structure extending vertically through the memory stack, a first dielectric layer on the memory stack, an etch stop layer on the first dielectric layer, a second dielectric layer on the etch stop layer, a first contact through the etch stop layer and the first dielectric layer and in contact with an upper end of the structure, and a second contact through the second dielectric layer and in contact with at least an upper end of the first contact.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, and a slit structure. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The slit structure extends vertically through the memory stack. An upper end of the slit structure is above an upper end of the channel structure.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.

Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.

Abstract: Embodiments of methods for forming channel holes in 3D memory devices using a nonconformal sacrificial layer are disclosed. In an example, a dielectric stack including interleaved first dielectric layers and second dielectric layers is formed on a substrate. An opening extending vertically through the dielectric stack is formed. A nonconformal sacrificial layer is formed along a sidewall of the opening, such that a variation of a diameter of the opening decreases. The nonconformal sacrificial layer and part of the dielectric stack abutting the nonconformal sacrificial layer are removed. A channel structure is formed in the opening after removing the nonconformal sacrificial layer and part of the dielectric stack.

Abstract: A forming method of an epitaxial layer, a forming method of a 3D NAND memory and an annealing apparatus are provided. In the forming method of the epitaxial layer, a first annealing process is performed for eliminating a stress generated in a stacked structure. When performing the first annealing process, a silicon-containing mixture is formed on a sidewall and a bottom surface of a trench. Thus, after performing the first annealing process, a second annealing process is performed for removing the silicon-containing mixture disposed at the sidewall and the bottom surface of the trench, such that when subsequently forming the epitaxial layer, a growth interface of the epitaxial layer is a pure substrate material interface, so as to prevent from be formed a void defect in the epitaxial layer formed in the trench.

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

Abstract: This invention relates to a semiconductor processing apparatus and a control method thereof. The semiconductor processing apparatus includes a processing chamber including two or more reaction regions. Each of the reaction regions includes an independent gas path module. The control method includes: cycle periods of introducing gas into the reaction regions are synchronized during the semiconductor processing. The semiconductor processing apparatus and the control method thereof of this invention can control the cycle periods of the reaction gas introduced into the reaction regions to be in consistent, so that the gas introduced into different reaction regions is the same at the same time, and the interference of the gas between the reaction regions is avoided, thereby improving the product yield.

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening.

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a bonded semiconductor device includes the following operations. First, a first wafer and a second wafer are formed. The first wafer can include a functional layer over a substrate. Single-crystalline silicon may not be essential to the substrate and the substrate may not include single-crystalline silicon. The first wafer can be flipped to bond onto the second wafer to form the bonded semiconductor device so the substrate is on top of the functional layer. At least a portion of the substrate can be removed to form a top surface of the bonded semiconductor device. Further, bonding pads can be formed over the top surface.