Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Abstract: In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.

Abstract: In one embodiment, an apparatus includes a power switch to provide a local power voltage at least one gated circuit based on a control signal. The apparatus also includes a delay sensor to provide a delay substantially equivalent to a processing delay of the at least one gated circuit. The apparatus also includes a phase detector to provide the control signal based at least in part on the delay.

Abstract: Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

Abstract: Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

Abstract: Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.

Abstract: A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, a data recovery circuit (DRC) including control logic to determine a phase control signal based on the first and the second phase shift indicators, and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.

Abstract: A squelch detector that differentially detects a presence of a communication signal on a communication channel. The squelch detector being coupled to outputs of a differential offset bias amplifier to receive differential offset biased signals and generate a differential direct current signal.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.

Abstract: A circuit provides a bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit.

Abstract: A method and apparatus are provided to generate calibration signals to multiple stages in a receiver channel. The multiple stages are calibrated using multiple calibration circuits, where a controller controls each calibration circuit. The controller is coupled to the output of the final stage in the receiver channel through a single comparison unit. The output from the single comparison unit is used by the controller to calibrate each of the multiple stages.

Abstract: Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: A system includes a locked loop circuit and a processor. The processor is coupled to the locked loop circuit to control the locked loop circuit and perform at least one other function in the system not related to the control of the locked loop circuit.

Abstract: Embodiments of a squelch detector are described herein.

Abstract: The present invention is directed to buffer/voltage mirror arrangement for sensitive node voltage connections.

Abstract: In accordance with certain described implementations, a voltage controlled oscillator (VCO) includes a VCO coarse tuning bank having multiple coarse tuning bank bits. Each coarse tuning bank bit has an associated bit capacitance. The bit capacitances of the coarse tuning bank bits may be selectively engaged using, for example, a single switching transistor for each coarse tuning bank bit.

Abstract: A method and apparatus to provide a reconfigurable differential dual port current conveyor circuit are described.

Abstract: In accordance with certain described implementations, a voltage controlled oscillator (VCO) includes a VCO coarse tuning bank having multiple coarse tuning bank bits. Each coarse tuning bank bit has an associated bit capacitance. The bit capacitances of the coarse tuning bank bits may be selectively engaged using, for example, a single switching transistor for each coarse tuning bank bit.