Patents by Inventor Hongjiang Song

Hongjiang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070002989
    Abstract: A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, a data recovery circuit (DRC) including control logic to determine a phase control signal based on the first and the second phase shift indicators, and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventor: Hongjiang Song
  • Patent number: 7139544
    Abstract: A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: November 21, 2006
    Assignee: Intel Corporation
    Inventors: Malcolm H Smith, Hongjiang Song
  • Patent number: 7042932
    Abstract: A method includes receiving an indication of incoming data from a first serial bus and buffering the bits to accommodate a difference between a first rate of the incoming data and a second rate of outgoing data. During the buffering, the method includes detecting if at least some of the bits indicate a synchronization field.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Publication number: 20060001490
    Abstract: A method and apparatus to provide a reconfigurable differential dual port current conveyor circuit are described.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventor: Hongjiang Song
  • Publication number: 20050221763
    Abstract: A method and apparatus are provided to generate calibration signals to multiple stages in a receiver channel. The multiple stages are calibrated using multiple calibration circuits, where a controller controls each calibration circuit. The controller is coupled to the output of the final stage in the receiver channel through a single comparison unit. The output from the single comparison unit is used by the controller to calibrate each of the multiple stages.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 6, 2005
    Inventor: Hongjiang Song
  • Patent number: 6917660
    Abstract: A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: July 12, 2005
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Publication number: 20050064839
    Abstract: A direct-down conversion receiver may include a transconductance-capacitor (GmC) filter to filter undesirable mixing products and provide a filtered baseband-differential signal. The GmC filter may include first and second transconductance-capacitor (GmC) circuits in series and a transconductance-feedback circuit in feedback with the second transconductance-capacitor circuit. The GmC circuits may comprise cross-coupled pairs of transistors to receive a baseband-differential signal and generate a differential output current. The GmC circuits may also comprise MOSCAPs coupled respectively between the differential inputs of the GmC circuit and internal-feedback nodes. In some embodiments, a substantially-constant bias voltage may be maintained across the voltage-dependent capacitors to allow the voltage-dependent capacitors to provide a substantially constant capacitance.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 24, 2005
    Inventors: Malcolm Smith, Hongjiang Song
  • Publication number: 20050062509
    Abstract: The present invention is directed to buffer/voltage mirror arrangement for sensitive node voltage connections.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 24, 2005
    Inventor: Hongjiang Song
  • Patent number: 6847236
    Abstract: The present invention is directed to buffer/voltage-mirror arrangements for sensitive node voltage connections.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: January 25, 2005
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Publication number: 20050003767
    Abstract: A circuit provides a bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit.
    Type: Application
    Filed: June 13, 2003
    Publication date: January 6, 2005
    Inventor: Hongjiang Song
  • Patent number: 6838945
    Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: January 4, 2005
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Patent number: 6775345
    Abstract: An apparatus including a sampling circuit to generate sampling clocks from a local clock and the sampling clocks to sample incoming data and a quarter clock, a phase detector to detect a phase difference between a data transition in sampled data and the local clock, and a delay line adapted to delay the sampled data by the detected phase difference.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Publication number: 20040037383
    Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.
    Type: Application
    Filed: August 19, 2003
    Publication date: February 26, 2004
    Inventor: Hongjiang Song
  • Patent number: 6639956
    Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: October 28, 2003
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Patent number: 6633248
    Abstract: A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: October 14, 2003
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Patent number: 6570931
    Abstract: An apparatus including a switched voltage bit cell (SVBC) array to receive an input voltage signal, each bit cell of the SVBC array configured to add a voltage to the input voltage signal and a delay locked-loop configured to delay an output voltage signal of each bit cell of the SVBC array by a determined step.
    Type: Grant
    Filed: December 31, 1999
    Date of Patent: May 27, 2003
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Patent number: 6531896
    Abstract: A method includes selecting either a current signaling mode or a voltage signaling mode to communicate with a serial bus. When the current signaling mode is selected, an output stage is placed in the current signaling mode, and when the voltage signaling mode is selected, the output stage is placed in the voltage signaling mode.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 11, 2003
    Assignee: Intel Corporation
    Inventor: Hongjiang Song
  • Publication number: 20030001766
    Abstract: A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 2, 2003
    Inventor: Hongjiang Song
  • Publication number: 20020181639
    Abstract: A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.
    Type: Application
    Filed: June 4, 2001
    Publication date: December 5, 2002
    Inventor: Hongjiang Song
  • Patent number: 6469646
    Abstract: A way of converting digital signals to analog signals is provided. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: October 22, 2002
    Assignee: Intel Corporation
    Inventor: Hongjiang Song