Patents by Inventor Hongyue Liu
Hongyue Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8422278Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.Type: GrantFiled: December 21, 2010Date of Patent: April 16, 2013Assignee: Seagate Technology LLCInventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
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Patent number: 8416614Abstract: A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.Type: GrantFiled: January 12, 2012Date of Patent: April 9, 2013Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Ran Wang, Dimitar V. Dimitrov
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Patent number: 8416615Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.Type: GrantFiled: May 18, 2012Date of Patent: April 9, 2013Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
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Patent number: 8411495Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.Type: GrantFiled: January 12, 2012Date of Patent: April 2, 2013Assignee: Seagate Technology LLCInventors: Hai Li, Yiran Chen, Hongyue Liu, Kang Yong Kim, Dimitar V. Dimitrov, Henry F. Huang
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Patent number: 8400825Abstract: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.Type: GrantFiled: June 8, 2012Date of Patent: March 19, 2013Assignee: Seagate Technologies LLCInventors: Xiaobin Wang, Haiwen Xi, Hongyue Liu, Insik Jin, Andreas Roelofs, Eileen Yan, Dimitar V. Dimitrov
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Patent number: 8400823Abstract: A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.Type: GrantFiled: May 5, 2010Date of Patent: March 19, 2013Assignee: Seagate Technology LLCInventors: Haiwen Xi, Hongyue Liu, Michael Xuefei Tang, Antoine Khoueir, Song S. Xue
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Patent number: 8391055Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.Type: GrantFiled: September 23, 2011Date of Patent: March 5, 2013Assignee: Seagate Technology LLCInventors: Xiaobin Wang, Yiran Chen, Alan Wang, Haiwen Xi, Wenzhong Zhu, Hai Li, Hongyue Liu
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Patent number: 8363449Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N?1 memory cells of the plurality via the common floating source line.Type: GrantFiled: August 10, 2011Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
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Patent number: 8363442Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.Type: GrantFiled: October 13, 2010Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Harry Hongyue Liu, Haiwen Xi, Antoine Khoueir, Song Xue
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Patent number: 8363450Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns. A selection circuit is provided that is capable of activating the first block of memory cells while deactivating the second block of memory cells. Further, a read circuit is provided that is capable of reading a logical state of a predetermined memory cell in the first block of memory cells with a reduced leak current by programming a first resistive state to the block selection elements corresponding to the first block of memory cells while programming a second resistive state to the block selection elements corresponding to the second block of memory cells.Type: GrantFiled: October 24, 2011Date of Patent: January 29, 2013Assignee: Seagate Technology LLCInventors: Chulmin Jung, Yong Lu, Insik Jin, YoungPil Kim, Harry Hongyue Liu
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Publication number: 20130003448Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
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Patent number: 8296620Abstract: A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold.Type: GrantFiled: August 26, 2008Date of Patent: October 23, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
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Patent number: 8289752Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.Type: GrantFiled: January 19, 2012Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Yong Lu, Harry Hongyue Liu
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Patent number: 8289804Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N?1 output lines.Type: GrantFiled: May 4, 2011Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
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Patent number: 8289759Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.Type: GrantFiled: April 21, 2011Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar V. Dimitrov, Wei Tian, Brian S. Lee
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Patent number: 8289746Abstract: A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.Type: GrantFiled: November 18, 2010Date of Patent: October 16, 2012Assignee: Seagate Technology LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Song S. Xue
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Publication number: 20120250405Abstract: Memory units that have a magnetic tunnel junction cell that utilizes spin torque and a current induced magnetic field to assist in the switching of the magnetization orientation of the free layer of the magnetic tunnel junction cell. The memory unit includes a spin torque current source for passing a current through the magnetic tunnel junction cell, the spin torque current source having a direction perpendicular to the magnetization orientations, and also includes a magnetic ampere field current source is oriented in a direction orthogonal or at some angles to the magnetization orientations.Type: ApplicationFiled: June 8, 2012Publication date: October 4, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Xiaobin Wang, Haiwen Xi, Hongyue Liu, Insik Jin, Andreas Roelofs, Eileen Yan, Dimitar V. Dimitrov
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Publication number: 20120230084Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.Type: ApplicationFiled: May 23, 2012Publication date: September 13, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
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Publication number: 20120230093Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
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Publication number: 20120224417Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.Type: ApplicationFiled: May 16, 2012Publication date: September 6, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang