Patents by Inventor Hongyue Liu

Hongyue Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NAND flash memory with integrated bit line capacitance
    Patent number: 8050092
    Abstract: Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: November 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Harry Hongyue Liu, Brian Lee, Yong Lu, Dadi Setiadi
  • Multi-stage parallel data transfer
    Patent number: 8045412
    Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: October 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu, Hai Li, Andrew John Carter, Daniel Reed
  • Bit set modes for a resistive sense memory cell array
    Patent number: 8040713
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: October 18, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT
    Publication number: 20110228598
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Write current compensation using word line boosting circuitry
    Patent number: 8009457
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
  • Asymmetric write current compensation using gate overdrive for resistive sense memory cells
    Patent number: 8009458
    Abstract: Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: August 30, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yong Lu, Harry Hongyue Liu
  • Semiconductor Control Line Address Decoding Circuit
    Publication number: 20110205830
    Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N?1 output lines.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
  • Floating source line architecture for non-volatile memory
    Patent number: 8004872
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • MAGNETIC FLOATING GATE MEMORY
    Publication number: 20110199832
    Abstract: An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.
    Type: Application
    Filed: April 28, 2011
    Publication date: August 18, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Yang Li, Hongyue Liu, Song S. Xue
  • Non-Volatile Memory Cell With Precessional Switching
    Publication number: 20110194337
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tian, Brian Seungwhan Lee
  • DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT
    Publication number: 20110194334
    Abstract: A memory array includes a cross-point array of bit and source lines. A memory is disposed at cross-points of the cross-point array. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. A transistor is electrically between the magnetic tunnel junction data cell and the bit line or source line and a diode is in thermal or electrical contact with the magnetic tunnel junction data cell to assist in resistance state switching.
    Type: Application
    Filed: April 15, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yiran Chen, Dimitar V. Dimitrov, Hongyue Liu, Xiaobin Wang
  • MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS
    Publication number: 20110194330
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Application
    Filed: April 18, 2011
    Publication date: August 11, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • SHARED BIT LINE AND SOURCE LINE RESISTIVE SENSE MEMORY STRUCTURE
    Publication number: 20110188301
    Abstract: A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Hai Li, Hongyue Liu
  • Current Cancellation for Non-Volatile Memory
    Publication number: 20110182106
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Application
    Filed: April 6, 2011
    Publication date: July 28, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter
  • Transmission gate-based spin-transfer torque memory unit
    Patent number: 7974119
    Abstract: A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: July 5, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Yong Lu, Yang Li
  • Write current compensation using word line boosting circuitry
    Patent number: 7974121
    Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: July 5, 2011
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Harry Hongyue Liu, Henry Huang, Ran Wang
  • APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD
    Publication number: 20110156115
    Abstract: Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Maroun Georges Khoury, Hongyue Liu, Brian Lee, Andrew John Gjevre Carter
  • Semiconductor control line address decoding circuit
    Patent number: 7969812
    Abstract: Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 28, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Dadi Setiadi, YoungPil Kim, Harry Hongyue Liu, Hyung-Kyu Lee
  • Generic non-volatile service layer
    Patent number: 7966581
    Abstract: Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: June 21, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Hai Li, Haiwen Xi, Hongyue Liu
  • Current cancellation for non-volatile memory
    Patent number: 7965565
    Abstract: A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: June 21, 2011
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Insik Jin, YoungPil Kim, Yong Lu, Harry Hongyue Liu, Andrew John Carter