Abstract: In one embodiment, a memory circuit comprises a pair of cross-coupled inverters configured to store a bit of data and a first transistor coupled to a first node of the pair of cross-coupled inverters. A plurality of transistors that form the pair of inverters have a first nominal threshold voltage. The first transistor is coupled to a first bit line, and has a second nominal threshold voltage that is lower than the first nominal threshold voltage. More specifically, in one embodiment, the first transistor is a write transistor and another write transistor having the second nominal threshold voltage is coupled to the other node of the pair of cross-coupled inverters.

Abstract: A flop circuit comprises a precharge circuit for precharging a first node in response to an occurrence of a first phase of a timing signal, and a discharge circuit for conditionally discharging the first node in response to an occurrence of a second phase of the timing signal depending upon a data input signal. The flop circuit further comprises a voltage retention circuit, such as a latch, configured to store a retained logic value that depends upon a logic value present at the first node during at least a portion of the second phase of the timing signal, and an output circuit configured to generate an output signal that depends upon the data input signal. The output circuit may be configured to drive the output signal in a first logic state when the first node is discharged regardless of the retained logic value, and may be configured to drive the output signal in a logic state that depends upon the retained logic value when the first node is charged.

Abstract: In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency ops. Other dependencies are tracked in a second dependency array. The first dependency array may evaluate quickly, to support back-to-back issuance of short execution latency ops and their dependent ops. The second array may evaluate more slowly than the first dependency array.

Abstract: In one embodiment, a compressor circuit has a carry-in input and input bits a, b, c, and d. The compressor circuit comprises a first multiplexor (mux) coupled to receive a value of input bit a and a complement of the value of input bit a as inputs and a value of the input bit b as a first selection control. The first mux has a first output. Coupled to receive a value of input bit c and a complement of the value of input bit c as inputs and a value of the input bit d as a second selection control, a second mux has a second output. A third mux is coupled to receive the first output and a complement of the first output as inputs and the second output as a third selection control, and the third mux has a third output. The fourth mux, coupled to receive a value of the third output and a complement of a value of the third output as inputs and the carry-in input as a fourth selection control, has a fourth output which is a sum output of the compressor circuit.

Abstract: In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result and is coupled to receive a least significant bit of each operand of the adder and a carry-in input to the adder. Each remaining logic circuit is coupled to receive a respective bit from the respective bit position of each operand and a less significant bit adjacent to the respective bit of each operand. Each logic circuit is configured to generate an output signal indicative of whether or not a specific result occurs in the respective bit position of the result responsive only to inputs that the logic circuit is coupled to receive as stated previously.

Abstract: In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. Coupled to receive the input operand and the shift count, the rotator is configured to rotate the input operand by the shift count. Coupled to receive the shift count and the shift direction, the mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to open and close responsive to respective pairs of control signals. The logic circuitry is coupled to receive a clock signal, a delayed clock signal, and mux select control signals, and is configured to generate pulses on the pair of control signals to control a passgate that has an input coupled to receive the signal representing a selected mux inputs, as indicated by the mux select control signals. The width of the pulses is dependent on the clock signal and the delayed clock signal. The latch element is configured to latch the signal representing the selected mux input in parallel with the selected mux input being driven as an output of the mux/storage circuit.

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: A carry look-ahead adder capable of adding or subtracting two input signals includes first stage logic having a plurality of carry-create and carry-transmit logic circuits each coupled to receive one or more bits of each input signal. Each carry-create circuit generates a novel carry-create signal in response to corresponding first bit-pairings of the input signals, and each carry-transmit circuit generates a novel carry-transmit signal in response to corresponding second bit-pairings of the input signals. The carry-create and carry-transmit signals are combined in carry look-ahead logic to generate accumulated carry-create signals, which are then used to select final sum bits.