Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: A heat dissipation device of electronic equipment has a base, a heat dissipation group, and a cover. The base has an opening, a chamber, and a boss formed in the chamber. The heat dissipation group is connected to the base and has a circuit board and a cooling blade. The circuit board is mounted in the chamber, abuts against the boss, and has a heat source area and at least one non-heat-source area. The heat source area has a first surface facing the boss and a second surface facing the opening. The cooling blade is connected to the base and is located at the second surface. The first surface and the second surface of the heat source area respectively correspond to the boss and the cooling blade in location to provide a guiding direction for heat conduction. The cover is connected to the base.

Abstract: A rotary bearing assembly is disclosed and includes an input shaft, an inner-ring component, an outer-ring component and a load element. The input shaft is configured to combine a rotating shaft of a motor to provide a power input. The inner-ring component includes a gear set, wherein the inner-ring component is sleeved on the input shaft through the gear set and driven by the input shaft. The outer-ring component is sleeved on the inner-ring component through a load element and engaged with the gear set, wherein when the gear set is driven by the input shaft to drive the inner-ring component, the gear set drives the outer-ring component, and the inner-ring component and the outer-ring component are rotated relatively, wherein one of the inner-ring component and the outer-ring component is served to provide a power output, and a rotational speed difference is between the power input and the power output.

Abstract: A light detecting device includes a substrate that has a lattice constant. A buffer layer is disposed on the substrate. A gradient layer is formed on the buffer layer opposite to the substrate, and includes a plurality of sublayers that have respectively lattice constants each of which is greater than the lattice constant of the substrate. The sublayers are arranged in a manner that the lattice constants of the sublayers undergo a gradual increase in lattice constant in a direction away from the substrate. A barrier layer is formed on the gradient layer opposite to the buffer layer, and has a lattice constant which is greater than that of the substrate and no smaller than the lattice constants of the sublayers. An absorption layer is formed on the barrier layer opposite to the gradient layer.

Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.

Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.

Abstract: An electronic device is provided. The electronic device includes a redistribution structure, an electronic unit and a first conductive pad. The first conductive pad is disposed between the redistribution structure and the electronic unit. The electronic unit is electrically connected to the redistribution structure through the first conductive pad. The first conductive pad has a first coefficient of thermal expansion and a first Young's modulus. The first coefficient of thermal expansion and the first Young's modulus conform to the following formula: 0.7×(0.0069E2?1.1498E+59.661)?CTE?1.3×(0.0069E2?1.1498E+59.661), wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula.

Abstract: Disclosed herein are methods of producing tumor antigen-specific T cells and uses thereof. In the present method, peripheral blood mononuclear cells (PBMCs) isolated from a subject are cultivated with bi-specific antibodies (BsAbs) in a culture medium so as to produce the tumor antigen-specific T cells from the PBMCs. Also provided in the present disclosure are tumor antigen-specific T cells produced by the present method, and uses thereof in treating subjects suffering from cancers.

Abstract: A package structure includes a first die and a second die embedded in a first molding material, a first redistribution structure over the first die and the second die, a second molding material over portions of the first die and the second die, wherein the second molding material is disposed between a first portion of the first redistribution structure and a second portion of the first redistribution structure, a first via extending through the second molding material, wherein the first via is electrically connected to the first die, a second via extending through the second molding material, wherein the second via is electrically connected to the second die and a silicon bridge electrically coupled to the first via and the second via.

Abstract: Provided is a composition for improving gut microbiota, including: a bacterial species combination consisting of Limosilactobacillus fermentum TCI275 with an accession number of BCRC 910940, Bifidobacterium animalis subsp. lactis TCI604 with an accession number of BCRC 910887, and Weizmannia coagulans TCI803 with an accession number of BCRC 910946. Provided is a method for improving gut microbiota of a subject in need thereof with the bacterial species combination.

Abstract: A fan module and computing device with the fan module are disclosed. The fan module includes a handle configured to actuate between an operation state and a release state. The handle in the release state allows a user to vertically remove the fan module from its respective fan module slot and away from the bottom panel.

Abstract: A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.

Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.

Abstract: The present disclosure provides a battery charging system and method. The battery charging method includes: determining a degree of healthy of a battery module according to an evaluation mechanism; setting a charging standard according to the degree of healthy; by handshaking with a charger, setting a charging voltage for the charger according to the charging standard to charge the battery module; and by the charger, perform a charging operation on the battery module until a fully charged condition is satisfied.

Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.

Abstract: Disclosed is a method for enhancing memory utilization and throughput of a computing platform in training a deep neural network (DNN). The critical features of the method includes: calculating a memory size for every operation in a computational graph, storing the operations in the computational graph in multiple groups with the operations in each group being executable in parallel and a total memory size less than a memory threshold of a computational device, sequentially selecting a group and updating a prefetched group buffer, and simultaneously executing the group and prefetching data for a group in the prefetched group buffer to the corresponding computational device when the prefetched group buffer is update. Because of group execution and data prefetch, the memory utilization is optimized and the throughput is significantly increased to eliminate issues of out-of-memory and thrashing.