Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.

Abstract: A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports.

Abstract: A power management system is described. The power management system includes an input power selecting unit, a charging control unit and a power switching control unit. The input power selecting unit receives a plurality of input power sources for selecting one of the input power sources to be inputted to the electronic apparatus. The charging control unit includes a charging controller and a battery. The charging controller receives a charge-enabling signal. The battery is charged by a second voltage and selectively supplies a battery power. The power switching control unit outputs a driving voltage to drive the electrical apparatus based on an adaptor-enabling signal and a power-detecting signal when the power switching control unit switches the input power sources and the battery power to select one of the input power sources and the battery power.

Abstract: An integrated data accessing system having control apparatus for multi-directional data transmission is described. The integrated data accessing system includes a control apparatus, a plurality of communication interface engines. The control apparatus includes a plurality of bi-directional transmission modules, a control unit, a multi-directional transferring engine, and a memory unit. The control unit detects a source storage and a target storage. The multi-directional transferring engine selectively transfers the data content among storage units. The multi-directional transferring engine includes a first switch module, a second switch module, and a data buffer. The first switch module switches to the first bi-directional transmission module to select the source storage. The second switch module switches to the second bi-directional transmission module to select the target storage. The data buffer stores the data content transmitted from the source storage and the target storage.

Abstract: A caching device is positioned between a memory read/write controller and a flash memory, which contains an instruction register, a logical address register, a data register, a pair of auxiliary controllers, a microprocessor, an address translation unit, a flash memory address register, a caching control unit, and a caching instruction and data buffer area. Among them, the microprocessor is the core of the caching device responsible not only for the reading and writing the flash memory but also for the caching operation for logical and physical address translation. The caching control unit is a programmable device containing the instruction and data for caching the logical and physical address mapping. The caching instruction and data buffer area temporarily stores the caching instruction and data used by the caching control unit.

Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Abstract: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and the address register are connected to a flash memory respectively for storing the access instructions and the addresses. The flash memory control circuit is connected to both instruction register and address register for controlling the access to the flash memory. The data register is connected to flash memory control circuit for loading data to be written to the flash memory. The encoder encodes the written data, and the ECC generator generates an ECC, which is written to the flash memory through the signal converter. The comparator and the arbitrator provide the comparison with ECC and informing decoder f suspicious bit values when data is read from the flash memory.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The caching mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.

Abstract: A processing unit, a portable electrical device and an auto-run method thereof are described. The processing unit of the portable electrical device has a kernel program memory area where a virtual memory device is established. Then, a virtual auto-run file is stored in the virtual memory device. When the portable electrical device is electrically connected to an electronic apparatus, the electronic apparatus automatically executes at least one predetermined operation on the portable electrical device according to the virtual auto-run file.

Abstract: A power management system is described. The power management system includes an input power selecting unit, a charging control unit and a power switching control unit. The input power selecting unit receives a plurality of input power sources for selecting one of the input power sources to be inputted to the electronic apparatus. The charging control unit includes a charging controller and a battery. The charging controller receives a charge-enabling signal. The battery is charged by a second voltage and selectively supplies a battery power. The power switching control unit outputs a driving voltage to drive the electrical apparatus based on an adaptor-enabling signal and a power-detecting signal when the power switching control unit switches the input power sources and the battery power to select one of the input power sources and the battery power.

Abstract: An integrated data accessing system having control apparatus for multi-directional data transmission is described. The integrated data accessing system includes a control apparatus, a plurality of communication interface engines. The control apparatus includes a plurality of bi-directional transmission modules, a control unit, a multi-directional transferring engine, and a memory unit. The control unit detects a source storage and a target storage. The multi-directional transferring engine selectively transfers the data content among storage units. The multi-directional transferring engine includes a first switch module, a second switch module, and a data buffer. The first switch module switches to the first bi-directional transmission module to select the source storage. The second switch module switches to the second bi-directional transmission module to select the target storage. The data buffer stores the data content transmitted from the source storage and the target storage.

Abstract: An automatic charging and power management device includes a charging control unit and at least one power switching control unit. The charging control unit is connected to a rechargeable battery and an input power source to control the charging operation to the rechargeable battery. The input power source can be a USB-interfaced power source or a rectification transformer based power source. The power switching control unit connects the input power source and is provided with at least one power input terminal, a charging control terminal, a charging voltage terminal, a system actuation switch, a system actuation terminal, a power type terminal, and at least one power output terminal. The charging control terminal and the charging voltage terminal are connected to the charging control unit. The system actuation terminal is actuated on/off by the system actuation switch to generate a system actuation signal. The power type terminal generates an identification signal based on the type of the input power source.

Abstract: A highly efficient data characteristic identification method for flash memory is provided, including the steps of: (a) based on the LBA corresponding to the write request to the flash memory, finding K corresponding counters in the hash table through K hash functions; (b) determining whether to perform decay period computation on hash table; if so, proceeding to step (c); otherwise, proceeding to step (d); (c) performing decay period computation on the hash table; (d) performing state update computation on the hash table; and (e) checking the hash table state and determining whether the data in the logic block corresponding to the flash memory is frequently updated. The method contains the decay period computation, state update computation, and checking on the data in the corresponding counters in the hash table to determine whether the data is frequently updated. Therefore, the object of a highly efficient data access characteristic identification method for flash memory is provided.

Abstract: A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block.

Abstract: Disclosed is a storage apparatus for digital TV video/analog TV video/digital audio broadcasting/analog audio broadcasting media (DTV/ATV/DAB/AAB). The storage apparatus comprises a controller, a DTV/ATV/DAB/AAB interface converter and at least one storage media interfaces. The controller has a plurality of terminals for controlling the storage apparatus. The DTV/ATV/DAB/AAB interface converter connects to one of the terminals and a digital/analog tuner to receive DTV/ATV/DAB/AAB signals and converts the DTV/ATV/DAB/AAB signals into DTV/ATV/DAB/AAB data. The storage media interfaces respectively connect to the terminals of the controller and to at least one portable storage media, for storing the DTV/ATV/DAB/AAB data received from the DTV/ATV/DAB/AAB interface converter into the portable storage media. The controller can be an OTG controller.

Abstract: A card reading apparatus integrating identification function is provided, including a USB interface, a memory card interface, an ATA/ATAPI interface, a USB OTG controller, an identification interface module, an encrypted identification processor, and at least an identification device. The USB interface, the memory card interface, and the ATA/ATAPI interface are connected respectively to a USB interface media device, a flash memory card, and a data storage device, such as hard disk or CD-RW. The USB OTG controller is connected to the USB interface, the memory card interface, and the ATA/ATAPI interface so that the USB interface media device, the flash memory card, and the data storage device can exchange data under the control of the USB OTG controller. The identification interface module is connected to the USB OTG controller, the encrypted identification processor is connected to the identification interface module, and the identification device is connected to the encrypted identification processor.

Abstract: An audio data storage and playback apparatus is provided, including at least a USB hub or USB SIE, at least a storage media interface, and an audio codec. An upstream port of the USB hub or the USB SIE is connected to an electronic device with a USB interface. The storage media interface is connected to a downstream port of the USB hub or an endpoint of a USB SIE. The storage media interface can be connected to a portable storage media, such as flash memory, CD-R/W, DVD-R/W, and hard disk drive, to enable bi-directional data transmission and storage between the electronic device with a USB interface and the portable storage media connected to the storage media interface. The audio codec player forms a bi-directional data transmission connection with the storage media interface. The audio codec player is connected to at least an audio player and an audio input device.

Abstract: A card reading apparatus for multi-directional data transmission is provided, including a USB interface, a memory card interface, an ATA/ATAPI interface, and a USB OTG controller. The USB OTG controller is connected to the USB interface, the memory card interface, and the ATA/ATAPI interface so that the USB media device connected to the USB interface, the flash memory cards connected to the memory card interface, and the data storage devices, such as hard disk and CD-R/W, connected to the ATA/ATAPI interface can all perform multi-directional data transfer among themselves.

Abstract: A highly efficient data characteristic identification device for flash memory is provided, including an instruction register, a plurality of auxiliary controllers, a data register, an address register, a microprocessor, a plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder. By connecting the instruction register, data register and address register to a flash memory access control circuit and flash memory for storing the control instruction of the access control circuit and the data and physical and logical address of the flash memory, the control instruction is decoded and transmitted by the microprocessor and the auxiliary controllers to each circuit. A plurality of hash function units, a hash table unit, a comparator, a shifter, and an adder form an index computation circuit for flash memory LBA. By using the index and computation on the contents of the hash function units, the data characteristics of the LBA can be stored with less memory and higher efficiency.