Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract: An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die.

Abstract: The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor.

Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.

Abstract: The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without introducing changes to process parameters used in fabrication of the FinFET MOS varactor. In some embodiments, the FinFET varactor circuit has a FinFET MOS varactor with a first terminal connected to a gate terminal of the FinFET MOS varactor and a second terminal connected to connected source and drain terminals of the FinFET MOS varactor. One or more control elements are connected to the first or second terminals of the FinFET MOS varactor and vary one or more operating characteristics of the FinFET MOS varactor. Using the control elements to vary the operating characteristics of the FinFET MOS varactor, allows for the characteristics to be adjusted without making changes to process parameters used in the fabrication of the FinFET MOS varactor.

Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.

Abstract: A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.

Abstract: A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.

Abstract: A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.

Abstract: A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.

Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

Abstract: A device comprises a radio frequency peak detector configured to receive an ac signal from a voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector and a feedback control unit coupled between an output of the radio frequency peak detector and an input of the voltage controlled oscillator.

Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.

Abstract: Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.