Patents by Inventor Hsieh-Hung Hsieh
Hsieh-Hung Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140145749Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.Type: ApplicationFiled: June 25, 2013Publication date: May 29, 2014Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8729968Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.Type: GrantFiled: May 9, 2011Date of Patent: May 20, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8664729Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.Type: GrantFiled: December 14, 2011Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Hsieh-Hung Hsieh
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Publication number: 20140055155Abstract: A semiconductor wafer includes a plurality of dies and at least one test probe. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit. The at least one test probe includes a plurality of probe pads. The plurality of probe pads is configured to transmit power signals and data to each of the plurality of dies, and to receive test results from each of the plurality of dies. The data are transmitted to each of the plurality of dies in a serial manner. The test results of each of the plurality of dies are also transmitted to the plurality of probe pads in a serial manner.Type: ApplicationFiled: October 18, 2012Publication date: February 27, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsiung Li, Kuang-Kai Yen, Yi-Hsuan Liu, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20140049329Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Luan Liu
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Publication number: 20130288443Abstract: Methods for forming reduced gate resistance finFETs. Methods for a metal gate transistor structure are disclosed including forming a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Additional methods are disclosed.Type: ApplicationFiled: June 26, 2013Publication date: October 31, 2013Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Hsieh-Hung Hsieh
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Publication number: 20130271223Abstract: A low-noise amplifier includes a first transistor having a gate configured to receive an oscillating input signal and a source coupled to ground. A second transistor has a source coupled to a drain of the first transistor, a gate coupled to a bias voltage, and a drain coupled to an output node. At least one of the first and second transistors includes a floating deep n-well that is coupled to an isolation circuit.Type: ApplicationFiled: April 13, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsieh-Hung HSIEH, Yi-Hsuan LIU, Chiao-Han LEE, Tzu-Jin YEH, Chewn-Pu JOU
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Publication number: 20130241634Abstract: An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.Type: ApplicationFiled: March 14, 2012Publication date: September 19, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung HSIEH, Yi-Hsuan LIU, Tzu-Jin YEH, Chewn-Pu JOU, Fu-Lung HSUEH
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Publication number: 20130154011Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.Type: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Hsieh-Hung Hsieh
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Patent number: 8451033Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.Type: GrantFiled: December 14, 2010Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yi Wu, Hsieh-Hung Hsieh, Ho-Hsiang Chen, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8427240Abstract: A low-noise amplifier (“LNA”) includes a first cascode gain stage including a first complementary metal oxide semiconductor (“CMOS”) transistor configured to receive a radio frequency (“RF”) input signal and a second CMOS transistor coupled to an output node. The first inductive gate network is coupled to a gate of the second CMOS transistor for increasing a gain of the first cascode gain stage. The first inductive gate network has a non-zero inductive input impedance and includes at least one passive circuit element.Type: GrantFiled: December 15, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Po-Yi Wu, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20120286836Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.Type: ApplicationFiled: May 9, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20120286888Abstract: A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.Type: ApplicationFiled: May 9, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8295018Abstract: An ESD protection circuit includes a signal pad, a short circuited shunt stub on-chip with and coupled to the signal pad, an open circuited shunt stub on-chip and coupled to the signal pad.Type: GrantFiled: July 26, 2010Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Po-Yi Wu, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8279008Abstract: A low-noise amplifier (LNA) includes a first cascode gain stage coupled to an input node for increasing an amplitude of an RF input signal. A first variable gain network is coupled to the first cascode gain stage and includes a first inductor for boosting a gain of the first cascode gain stage, a first capacitor coupled to the first inductor for blocking a direct current (DC) voltage, and a first switch coupled to the first inductor and to the first capacitor. The first switch is configured to selectively couple the first inductor to the first cascode gain stage in response to a first control signal.Type: GrantFiled: August 6, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Po-Yi Wu, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20120212865Abstract: A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming Hsien TSAI, Jun-De JIN, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Publication number: 20120146747Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Yi WU, Hsieh-Hung HSIEH, Ho-Hsiang CHEN, Tzu-Jin YEH, Chewn-Pu JOU, Fu-Lung HSUEH
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Publication number: 20120126630Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Fan-Ming KUO, Huan-Neng CHEN, Ming Hsien TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Publication number: 20120122395Abstract: Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.Type: ApplicationFiled: November 15, 2010Publication date: May 17, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Jin YEH, Hsieh-Hung HSIEH, Jun-De JIN, Ming Hsien TSAI, Chewn-Pu JOU, Fu-Lung HSUEH
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Publication number: 20120068745Abstract: A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is electrically connected to the differential direct injection pair and produces an operating frequency based on the mixed differential injection signals.Type: ApplicationFiled: September 22, 2010Publication date: March 22, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH