Abstract: A method and apparatus for receiving an input data; configuring the input data into a multiple arrayed data block; configuring the multiple arrayed data block into a plurality of data sub-blocks; recording non-zero values of the data sub-blocks; arranging the data block into a first bit mask block; dividing the first bit mask block into sub-block mask(s); packing or compressing sub-block masks with non-zero cell contents, wherein sub-block masks with all-zero cell contents are not packed; assigning indices or location indicators to the packed sub-block masks; and storing the packed sub-block masks and corresponding indices or location indicators.

Abstract: A method, system, and program product accesses chunks of data identifying data elements. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements are processed based on the mask. For compression of data, data elements in chunks of data that have zero values and that have non-zero values are determined. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements in the chunks of data having zero values are removed. The data elements having non-zero values are packed into the chunks to form the compressed data. For decompressing the data, zero-value data elements are added in positions in the chunks of data according to the mask to form uncompressed data.

Abstract: A method, system, and program product accesses chunks of data identifying data elements. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements are processed based on the mask. For compression of data, data elements in chunks of data that have zero values and that have non-zero values are determined. A mask is used to identify a position of the data elements that have zero values and that have non-zero values. The data elements in the chunks of data having zero values are removed. The data elements having non-zero values are packed into the chunks to form the compressed data. For decompressing the data, zero-value data elements are added in positions in the chunks of data according to the mask to form uncompressed data.

Abstract: A method, system and program product includes examining elements of a first matrix in a sequential fashion. Values of the examined elements are determined. A corresponding bit of a first mask is set to a first value if a determined value is zero. A corresponding bit of a first mask is set to a second value if a determined value is non-zero. The non-zero values are packed in a first vector, wherein bits of at least the first mask determine operations on packed values.

Abstract: A method, system and program product includes examining elements of a first matrix in a sequential fashion. Values of the examined elements are determined. A corresponding bit of a first mask is set to a first value if a determined value is zero. A corresponding bit of a first mask is set to a second value if a determined value is non-zero. The non-zero values are packed in a first vector, wherein bits of at least the first mask determine operations on packed values.

Abstract: A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.

Abstract: A heterogeneous computing system described herein has an energy-efficient architecture that exploits producer-consumer locality, task parallelism and data parallelism. The heterogeneous computing system includes a task frontend that dispatches tasks and updated tasks from queues for execution based on properties associated with the queues, and execution units that include a first subset acting as producers to execute the tasks and generate the updated tasks, and a second subset acting as consumers to execute the updated tasks. The execution units includes one or more control processors to perform control operations, vector processors to perform vector operations, and accelerators to perform multimedia signal processing operations. The heterogeneous computing system also includes a memory backend containing the queues to store the tasks and the updated tasks for execution by the execution units.

Abstract: A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.

Abstract: An image data processing method is provided. The image data processing method includes the following steps: receiving image data, wherein the image data is in a first pixel format; shuffling the image data according to a relationship between the first pixel format and a second pixel format to generate shuffled data; and compressing the shuffled data by a compression module which is suitable for compressing image data in the second pixel format so as to generate compressed data.

Abstract: A heterogeneous computing system described herein has an energy-efficient architecture that exploits producer-consumer locality, task parallelism and data parallelism. The heterogeneous computing system includes a task frontend that dispatches tasks and updated tasks from queues for execution based on properties associated with the queues, and execution units that include a first subset acting as producers to execute the tasks and generate the updated tasks, and a second subset acting as consumers to execute the updated tasks. The execution units includes one or more control processors to perform control operations, vector processors to perform vector operations, and accelerators to perform multimedia signal processing operations. The heterogeneous computing system also includes a memory backend containing the queues to store the tasks and the updated tasks for execution by the execution units.

Abstract: A multi-hierarchy interconnect system for a cache system having a tag memory and a data memory includes an address interconnect scheduling device and a data interconnect scheduling device. The address interconnect scheduling device performs a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory. The data interconnect scheduling device performs a data bank arbitration to schedule data requests to a plurality of data banks of the data memory. Besides, a multi-hierarchy interconnect method for a cache system having a tag memory and a data memory includes: performing a tag bank arbitration to schedule address requests to a plurality of tag banks of the tag memory, and performing a data bank arbitration to schedule data requests to a plurality of data banks of the data memory.

Abstract: A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.

Abstract: A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.

Abstract: A processing unit includes one or more first cores. The one or more first cores and one or more second cores are part of a heterogeneous computing system and share a system memory. Each first core includes a 1st L1 cache that supports snooping by the second cores, and a 2nd L1 cache that does not support snooping. The 1st L1 cache is coupled to and receives cache access requests from an instruction-based computing module of the first core, and the 2nd L1 cache is coupled to and receives cache access requests from a fixed-function pipeline module of the first core. The processing unit also includes a L2 cache that supports snooping. The L2 cache receives cache access requests from the 1st L1 cache and the 2nd L1 cache.

Abstract: A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.

Abstract: A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.

Abstract: A graphics processing system includes a first storage device, a second storage device, a vertex position shader, a vertex classification module, and a vertex attribute shader. The vertex position shader performs vertex position shading for vertices of primitives in a frame at a binning process. The vertex classification module classifies the vertices of the primitives in the frame into first-type vertices and second-type vertices according to vertex distribution. The vertex attribute shader performs deferred vertex attribute shading for the first-type vertices and the second-type vertices at a rendering process following the binning process, wherein vertex attribute shading results of at least a portion of the first-type vertices classified by the vertex classification module are stored in the second storage device, and vertex attribute shading results of at least a portion of the second-type vertices classified by the vertex classification module are stored in the first storage device.

Abstract: Embodiments of the invention disclose an image data processing method and an image data processing apparatus and a method and an apparatus for image data processing. The image data processing method includes the following steps: receiving image data, wherein said image data is in a first pixel format; shuffling said image data according to a relationship between the first pixel format and a second pixel format to generate shuffled data; and compressing said shuffled data by a compression module which is suitable for compressing image data in said second pixel format so as to generate compressed data.

Abstract: A storage system includes a data storage device having a plurality of data storage lines, a tag storage device having a plurality of address tags each associated with one data storage line allocated in the data storage device, and a controller. The controller sets a first number of address tags and configures a first number of data storage lines to serve as a first data storage line with a first data storage line size, and sets a second number of address tags and configures a second number of data storage lines to serve as a second data storage line with a second data storage line size. The second data storage line size is different from the first data storage line size.

Abstract: A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.