Abstract: A method and apparatus for efficiently rejecting a graphics primitive that is not visible in a defined area having a maximum x and y-coordinate. A data calculation block is configured to perform the rejection calculation on two levels. In the first level, the data calculation block determines if the graphics primitive is outside of the defined area or outside of the view frustum. This determination can take as little as one clock cycle. In the second level, the data calculation block determines whether the primitive is visible based on a vector normal to the primitive and the direction of culling. This determination may take as many as five clock cycles. When many of the rejections can be performed at the first level, there is a large performance increase. Furthermore, the sooner a rejection is determined, the sooner a new primitive can be processed by the data calculation block.

Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.

Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.

Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.

Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

Abstract: A method and apparatus for managing power consumption in logic modules without causing power surges. A first and second logic module operate in response to a first and second clock signal, respectively, to carry out a command. When the command arrives, the first logic module begins to operate and indicates that it is busy. After a first delay, the second module begins to operate and indicates that it is busy. When both modules are finished and no new command is available, the busy indicators are deactivated and after a second delay the first clock signal is deactivated. A third delay after the first clock signal is deactivated, the second clock is deactivated. The first, second and third delays are programmable to avoid power surges in the respective modules.

Abstract: Method and system for controlling the dynamic latency of an arithmetic logic unit (ALU). In one embodiment, the identification of the destination operand of an instruction is stored in a temporary register ID/thread control ID pair pipeline if the destination operand is a temporary register. Furthermore, each source operand of an instruction is checked against the identifications stored in a group of temporary register ID/thread control ID pipelines. If a source operand is matched to an identification stored in the temporary register ID/thread control ID pipelines, the ALU does not execute the instruction until the matched identification is no longer matched in the pipelines.

Abstract: Method and system for a dynamic FIFO flow control circuit. The dynamic FIFO flow control circuit detects one or more obsolete entries in a FIFO memory, retrieves the address of the next valid read pointer, and reads from the retrieved address during the next read operation.

Abstract: A system and method for processing a graphics primitive for display in a display area defined by a scissoring window. The graphics primitive is part of an object in view space which also includes a near and a far plane and possibly one or more user-defined clipping planes. These planes may affect the portion of the graphics primitive to be rendered in the display area. The graphics primitive is enclosed by a bounding box, which is then reduced, if possible, based on the Znear clipping plane intersecting the graphics primitive. The reduced bounding box is then subjected to the scissoring window if a portion of the bounding box lies outside the window. The final bounding box determines how much of the graphics primitive should be rendered in the display area. This reduces the amount of rendering that is required of the graphics system, and increases the performance of the system.

Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.

Abstract: A method and apparatus for efficiently rejecting a graphics primitive that is not visible in a defined area having a maximum x and y-coordinate. A data calculation block is configured to perform the rejection calculation on two levels. In the first level, the data calculation block determines if the graphics primitive is outside of the defined area or outside of the view frustum. This determination can take as little as one clock cycle. In the second level, the data calculation block determines whether the primitive is visible based on a vector normal to the primitive and the direction of culling. This determination may take as many as five clock cycles. When many of the rejections can be performed at the first level, there is a large performance increase. Furthermore, the sooner a rejection is determined, the sooner a new primitive can be processed by the data calculation block.

Abstract: A method and apparatus for managing power consumption in logic modules without causing power surges. A first and second logic module operate in response to a first and second clock signal, respectively, to carry out a command. When the command arrives, the first logic module begins to operate and indicates that it is busy. After a first delay, the second module begins to operate and indicates that it is busy. When both modules are finished and no new command is available, the busy indicators are deactivated and after a second delay the first clock signal is deactivated. A third delay after the first clock signal is deactivated, the second clock is deactivated. The first, second and third delays are programmable to avoid power surges in the respective modules.

Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.

Abstract: A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller selects a memory to store the index and assigns a thread id to the index, the thread id indicating in which memory the index is stored. The thread id is stored in both a HEAD ID FIFO and a DATA ID FIFO, to maintain the order of the primitives during processing. A first multiplexer accesses a selected memory based on a thread id provided by the HEAD ID FIFO and a second multiplexer accesses a selected memory based on a thread id provided by the DATA ID FIFO. For each of the vertices of the graphics primitive, the first multiplexer provides a pointer for accessing coordinate information and the second multiplexer provides a pointer for accessing attribute information.

Abstract: A system for enabling communications between a first circuit block and a second circuit block of a processing system is described. The system has a plurality of registers for storing data from the first block. A steering circuit enables data to be written to one of the plurality of registers depending on the value of a write pointer signal. The data is only written to one the registers selected by the write pointer signal if that register is empty. The system also has a multiplexer to read the data from one of the plurality of registers in response to a read pointer signal. The data is only read from one of the registers selected by the read pointer signal if that register is full. The write and read pointers are each advanced so as to select the register to be written or read in a circular fashion.

Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.