Patents by Inventor Hsin Cheng
Hsin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984110Abstract: A device operates to perform acoustic echo cancellation. The device includes a speaker to output a far-end signal at the device, a microphone to receive at least a near-end signal and the far-end signal from the speaker to produce a microphone output, and an AI accelerator operative to perform neural network operations according to a first neural network model and a second neural network model to output an echo-suppressed signal. The device further includes a digital signal processing (DSP) unit. The DSP unit is operative to perform adaptive filtering to remove at least a portion of the far-end signal from the microphone output to generate a filtered near-end signal, and perform Fast Fourier Transform (FFT) and inverse FFT (IFFT) to generate input to the first neural network model and the second neural network model, respectively.Type: GrantFiled: March 7, 2022Date of Patent: May 14, 2024Assignee: MEDIATEK SINGAPORE PTE. LTD.Inventors: Xiaoxi Yu, Hantao Huang, Ziang Yang, Chia Hsin Yang, Li-Wei Cheng
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Patent number: 11982936Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.Type: GrantFiled: June 30, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
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Publication number: 20240154016Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Chi On Chui
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Patent number: 11978740Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.Type: GrantFiled: February 17, 2022Date of Patent: May 7, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
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Patent number: 11975243Abstract: The present disclosure is relates to a TPU ball structure and a manufacturing method thereof. The TPU ball structure includes a ball bladder layer, a yarn layer and a surface layer. The ball bladder layer is made of TPU material. The yarn layer is made of TPU material, and the yarn layer is disposed to cover the ball bladder layer. The surface layer is made of TPU material, and the surface layer is disposed to cover the yarn layer. The above layers of the TPU ball structure are made of TPU material to satisfy a requirement for environmental protection, and are recyclable. There is no need to use adhesive to adhere the above layers of the TPU ball structure. Therefore, the peeling strength between the layers of the TPU ball structure can be increased so that the whole peeling strength of the TPU ball structure can be increased.Type: GrantFiled: April 22, 2021Date of Patent: May 7, 2024Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Chi-Chin Chiang, Wen-Hsin Tai
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Patent number: 11977250Abstract: A lighting keyboard includes a backlight module and at least one keyswitch. The backlight module includes a lighting substrate and a protruding structure. The lighting substrate includes two non-intersecting traces and a light emitting unit. The light emitting unit is connected between the two non-intersecting traces. A position of the protruding structure corresponds to a position of the light emitting unit and the protruding structure is located between the two non-intersecting traces. The at least one keyswitch is disposed on the backlight module.Type: GrantFiled: March 30, 2023Date of Patent: May 7, 2024Assignee: DARFON ELECTRONICS CORP.Inventors: Ying-Lan Liu, Hsin-Cheng Ho, Heng-Yi Huang
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Publication number: 20240147651Abstract: A hard disk bracket configured to be installed on a case includes a tray, a base, a handle, a pin, and a latch. The tray has an accommodating space. The base is connected to the tray. The handle is disposed in the base and has a first slide part detachably fastened with the base. The pin is disposed through the handle and the base. The latch is disposed in the base and is detachably fastened with the case. The latch is fastened with the handle and has a second slide part penetrating the handle for extending outside the base.Type: ApplicationFiled: August 10, 2023Publication date: May 2, 2024Applicant: PEGATRON CORPORATIONInventors: Wei-Cheng Liu, Hsin-Kai Chuang
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Publication number: 20240142459Abstract: A biological particle analysis method is provided and includes the following steps: fluorescence staining a liquid specimen through a fluorescence staining process so as to enable a target biological particle in the liquid specimen to becomes a fluorescence; accommodating the liquid specimen into a pico-droplet generator and using a camera device to take a real-time image of the liquid specimen; using the pico-droplet generator to output a target pico-droplet having the target biological particle onto a biochip according to the real-time image; removing the fluorescent color of the target biological particle in the target pico-droplet through a washing process; and fluorescence staining the target biological particle captured by the biochip at multiple times through the fluorescence staining process and the washing process, so as to obtain a plurality of fluorescence images respectively corresponding to multiple kinds of biological characterization expressions.Type: ApplicationFiled: April 10, 2023Publication date: May 2, 2024Inventors: Chung-Er Huang, Sheng-Wen Chen, Hsin-Cheng Ho, GUANG-CI YE
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Publication number: 20240139734Abstract: A biological particle enrichment apparatus and a pico-droplet generator thereof are provided. The pico-droplet generator includes a container, a hollow needle connected to the container, a first piezoelectric member disposed on the container, and a second piezoelectric member disposed on the hollow needle. The container can receive a liquid specimen having biological particles. The hollow needle and the container are fluid communicated with each other, and an inner diameter of the container is within a range from 5 times to 30 times of an inner diameter of the hollow needle. The first piezoelectric member is annularly disposed on a surrounding lateral side of the container, and enables the biological particles in the container to move along a direction away from the surrounding lateral side by vibrating the container. The second piezoelectric member can squeeze the hollow needle, so that the liquid specimen flows outwardly to form a pico-droplet.Type: ApplicationFiled: April 10, 2023Publication date: May 2, 2024Inventors: Chung-Er Huang, Sheng-Wen Chen, Hsin-Cheng Ho, GUANG-CI YE
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Patent number: 11974311Abstract: A method for wireless communication performed by a user equipment (UE) is provided. The method includes receiving, from a base station (BS), a Radio Resource Control (RRC) configuration to configure a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and generating first uplink control information (UCI) in response to the first SPS PDSCH, where the RRC configuration includes a first parameter that indicates a priority of the first UCI.Type: GrantFiled: March 1, 2023Date of Patent: April 30, 2024Assignee: Hannibal IP LLCInventors: Wan-Chen Lin, Yu-Hsin Cheng, Heng-Li Chin, Hsin-Hsi Tsai
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Patent number: 11974302Abstract: A method and a User Equipment (UE) for beam operations are provided. The method includes monitoring at least one of a plurality of Control Resource Sets (CORESETs) configured for the UE within an active Bandwidth Part (BWP) of a serving cell in a time slot; and applying a first Quasi Co-Location (QCL) assumption of a first CORESET of a set of one or more of the monitored at least one of the plurality of CORESETs to receive a Downlink (DL) Reference Signal (RS), wherein the first CORESET is associated with a monitored search space configured with a lowest CORESET Identity (ID) among the set of one or more of the monitored at least one of the plurality of CORESETs.Type: GrantFiled: April 6, 2023Date of Patent: April 30, 2024Assignee: Hannibal IP LLCInventors: Chien-Chun Cheng, Tsung-Hua Tsai, Yu-Hsin Cheng, Wan-Chen Lin
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Publication number: 20240134268Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
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Patent number: 11965217Abstract: A method and a kit for detecting Mycobacterium tuberculosis are provided. The method includes a step of performing a nested qPCR assay to a specimen. The nested qPCR assay includes a first round of amplification using external primers and a second round of amplification using internal primers and a probe. The external primers have sequences of SEQ ID NOs. 1 and 2, and the internal primers and the probe have sequences of SEQ ID NOs. 3 to 5.Type: GrantFiled: May 24, 2021Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yi-Chen Li, Chih-Cheng Tsou, Min-Hsien Wu, Hsin-Yao Wang, Chien-Ru Lin
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Publication number: 20240128232Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Publication number: 20240130055Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yuan-Cheng HUANG, I-Hung CHIANG, Ji-Yuan SYU, Hsin-Han LIN, Po-Kai CHIU, Kuo-Shu KAO
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Patent number: 11963117Abstract: A method performed by a wireless communication device includes determining whether to transmit a first Sidelink Synchronization Signal (SLSS) according to a priority parameter when an occasion of the first SLSS collides with a Physical Sidelink Feedback Channel (PSFCH) that carries Sidelink Feedback Control Information (SFCI). The priority parameter is associated with a Physical Sidelink Shared Channel (PSSCH) that corresponds to the PSFCH.Type: GrantFiled: September 13, 2022Date of Patent: April 16, 2024Assignee: Hannibal IP LLCInventors: Yu-Hsin Cheng, Tsung-Hua Tsai, Chie-Ming Chou, Yung-lan Tseng
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Patent number: 11961808Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.Type: GrantFiled: October 14, 2021Date of Patent: April 16, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wei-Jen Wang, Po-Jen Cheng, Fu-Yuan Chen, Yi-Hsin Cheng
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Patent number: 11960201Abstract: The present disclosure describes a method of patterning a semiconductor wafer using extreme ultraviolet lithography (EUVL). The method includes receiving an EUVL mask that includes a substrate having a low temperature expansion material, a reflective multilayer over the substrate, a capping layer over the reflective multilayer, and an absorber layer over the capping layer. The method further includes patterning the absorber layer to form a trench on the EUVL mask, wherein the trench has a first width above a target width. The method further includes treating the EUVL mask with oxygen plasma to reduce the trench to a second width, wherein the second width is below the target width. The method may also include treating the EUVL mask with nitrogen plasma to protect the capping layer, wherein the treating of the EUVL mask with the nitrogen plasma expands the trench to a third width at the target width.Type: GrantFiled: May 15, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Cheng Hsu, Chun-Fu Yang, Ta-Cheng Lien, Hsin-Chang Lee
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Publication number: 20240121718Abstract: Some of the present implementations provide a method for a user equipment (UE) for receiving a power saving signal. The method receives, from a base station, a power saving signal comprising a minimum applicable K0 (K0min) that indicates a minimum scheduling offset restriction between a physical downlink control channel (PDCCH) and a physical downlink shared channel (PDSCH). The method determines an application delay based on a predefined value. The method then applies the minimum scheduling offset restriction after the application delay.Type: ApplicationFiled: October 23, 2023Publication date: April 11, 2024Inventors: Yu-Hsin Cheng, Chie-Ming Chou, Wan-Chen Lin, Tsung-Hua Tsai
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Patent number: 11955384Abstract: A device includes a bottom transistor, a top transistor, and an epitaxial isolation structure. The bottom transistor includes a first channel layer, first source/drain epitaxial structures, and a first gate structure. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The first gate structure is around the first channel layer. The top transistor is over the bottom transistor and includes a second channel layer, second source/drain epitaxial structures, and a second gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer. The second gate structure is around the second channel layer. The epitaxial isolation structure is between and in contact with one of the first source/drain epitaxial structures and one of the second source/drain epitaxial structures, such that the one of the first source/drain epitaxial structures is electrically isolated from the one of the second source/drain epitaxial structures.Type: GrantFiled: February 17, 2022Date of Patent: April 9, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITYInventors: Chien-Te Tu, Hsin-Cheng Lin, Chee-Wee Liu