Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: An image downsampling apparatus and an image downsampling method are provided. The image downsampling apparatus includes a one-directional downsampling circuit, a multi-directional downsampling circuit and an output circuit. The one-directional downsampling performs one-directional downsampling by using an original image signal to obtain and output a first adjusted image signal. The multi-directional downsampling circuit performs multi-directional downsampling by using the original image signal to obtain and output a second adjusted image signal. The output circuit outputs a downsampled image signal according to the first adjusted image signal and the second adjusted image signal.

Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.

Abstract: An image downsampling apparatus and an image downsampling method are provided. The image downsampling apparatus includes a one-directional downsampling circuit, a multi-directional downsampling circuit and an output circuit. The one-directional downsampling performs one-directional downsampling by using an original image signal to obtain and output a first adjusted image signal. The multi-directional downsampling circuit performs multi-directional downsampling by using the original image signal to obtain and output a second adjusted image signal. The output circuit outputs a downsampled image signal according to the first adjusted image signal and the second adjusted image signal.

Abstract: The present invention provides a Hemoglobin A1c-specific aptamer and a Hemoglobin-specific aptamer. The aptamers were selected in vitro using SELEX and a microfluidic chip system. The aptamers established low free energy, thus were more stable than conventional antibodies. The high specificity of the aptamers to Hemoglobin A1c or Hemoglobin allows them to be effectively used in diagnosis of diabetes and/or anemia.

Abstract: A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed.

Abstract: The present invention provides a Hemoglobin A1c-specific aptamer and a Hemoglobin-specific aptamer. The aptamers were selected in vitro using SELEX and a microfluidic chip system. The aptamers established low free energy, thus were more stable than conventional antibodies. The high specificity of the aptamers to Hemoglobin A1c or Hemoglobin allows them to be effectively used in diagnosis of diabetes and/or anemia.

Abstract: A signal adjusting circuit and a video apparatus thereof are provided. The signal adjusting circuit includes a delay unit, a minimum value acquisition device, and a first operating unit. The delay unit receives a digital signal and delays the digital signal for N periods to serve as a delay signal. The minimum value acquisition device receives the digital signal and acquires a minimum value of the digital signal in every N periods. The first operating unit is coupled to the delay unit and the minimum value acquisition device for operating the delay signal with the minimum value to obtain an adjusting signal.

Abstract: A noise estimator device of a video decoder includes a reception end, a low pass filter coupled to the reception end, a delay unit coupled to the reception end, a minimum level estimation unit coupled to the low pass filter for estimating a minimum of a specific number of low-pass results, a difference level estimation unit coupled to the low pass filter, the delay unit, and the minimum level estimation unit for determining a synchronization signal according to a plurality of low-pass results and the minimum of the specific number of the low-pass results, and for estimating a noise level according to the synchronization signal and signals outputted from the delay unit, and an output end coupled to the difference level estimation unit.

Abstract: An aptamer specifically binding to C-reactive protein (CRP) is provided. The aptamer includes a following nucleotide sequence: 5?-angngggngnntgnnt-3?, wherein n is a nucleotide selected from a, t, c and g.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: A slicer level calculator including a signal detector, a moving average calculator, a sync-tip voltage sample circuit, a blanking voltage sample circuit, a slicer level calculator, and a rear-end processor is disclosed. The signal detector determines whether an input video signal satisfies a low signal to noise ratio (SNR) criterion. If so, the first signal detector further enables a low SNR control signal. The moving average calculator obtains a moving average voltage level of the input video signal. The sync-tip voltage sample circuit, the blanking voltage sample circuit and the slicer level calculator obtain a sync-tip voltage level, a blanking voltage level, and a slicer voltage level, respectively. The rear-end processor selectively executes low-pass filtering operation on the slicer voltage level in response to the low SNR control signal.

Abstract: A state detector of a video device and a state detection method thereof are provided. The state detector includes a first chroma detector, a second chroma detector, and a controller. The first chroma detector and the second chroma detector operate in a first state among a plurality of states. When the second chroma detector is not capable of processing an input signal normally, the controller controls the second chroma detector to switch between the states until the second chroma detector operates in a second state to process the input signal normally, and the first chroma detector is set to operating in the second state. As a result, the quality of a displayed image is improved.

Abstract: An apparatus and a method for filtering noise in an image signal are provided. The apparatus includes an analog-to-digital converter (ADC), a first filter, and a second filter. The ADC receives the image signal and converts the image signal into a digital signal. The first filter receives the digital signal and filters a first noise portion of the digital signal to generate a first signal. The second filter coupled to the first filter receives the first signal and filters a second noise portion of the first signal, wherein the first noise portion is a sampled-based impulse noise, and the second noise portion is a line-based impulse noise.

Abstract: A slicer level calculator including a signal detector, a moving average calculator, a sync-tip voltage sample circuit, a blanking voltage sample circuit, a slicer level calculator, and a rear-end processor is disclosed. The signal detector determines whether an input video signal satisfies a low signal to noise ratio (SNR) criterion. If so, the first signal detector further enables a low SNR control signal. The moving average calculator obtains a moving average voltage level of the input video signal. The sync-tip voltage sample circuit, the blanking voltage sample circuit and the slicer level calculator obtain a sync-tip voltage level, a blanking voltage level, and a slicer voltage level, respectively. The rear-end processor selectively executes low-pass filtering operation on the slicer voltage level in response to the low SNR control signal.

Abstract: A video signal processing circuit includes: a transport stream (TS) decoding unit, decoding a demodulated analog radio frequency (RF) signal for generating a first TS signal; and a TS bit rate control unit, deciding whether to insert a null packet stream into the first TS signal to generate a second TS signal.

Abstract: A video signal processing circuit includes: a composite sync signal generation circuit, generating a composite sync signal from a received composite video signal; a signal-noise-ratio calculation unit, generating a SNR of the composite video signal; a timing generation unit, generating a gated window based on the SNR; and a vertical sync signal separation unit, generating a vertical sync signal from the composite sync signal based on the SNR and the gated window, and dynamically adjusting a detection criterion on the vertical sync signal.

Abstract: An aptamer specifically binding to C-reactive protein (CRP) is provided. The aptamer includes a following nucleotide sequence: 5?-angngggngnntgnnt-3?, wherein n is a nucleotide selected from a, t, c and g.

Abstract: A method for enhancing data rate of an advanced micro-controller bus architecture (AMBA) having an AHB system and an APB system includes simultaneously receiving control signals outputted from a plurality of master devices of the AHB system, and controlling a plurality of peripheral slave devices of the APB system according to the control signals outputted from the plurality of master devices.