Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract: A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Abstract: A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.

Abstract: A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

Abstract: A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.

Abstract: A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

Abstract: A method of forming a bottle-shaped trench for capacitor in a semiconductor substrate. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. Then, an oxide film is formed on the top portion of the trench. Next, a rugged polysilicon layer is formed on the bottom portion and the top portion of the trench. The rugged polysilicon layer and the semiconductor substrate are etched through the bottom portion of the trench by diluted ammonia solution as the etchant to form a bottle-shaped trench having a rugged surface. Next, the oxide film is removed.

Abstract: A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.

Abstract: A method of reworking an integrated circuit device is described. A substrate having a dielectric layer, a barrier layer, a conductive layer and an anti-reflective layer formed thereon, is provided. The method of reworking the barrier layer, the conductive layer and the anti-reflective layer comprises removing the anti-reflection layer by performing a dry etching process, removing the conductive layer by performing a wet etching process, and then removing the barrier layer by performing a chemical machine polishing process.

Abstract: A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

Abstract: A method of forming a high aspect ratio shallow trench isolation in a semiconductor substrate. The method includes the steps of forming a hard mask layer with a certain pattern on the semiconductor substrate, etching a portion of the semiconductor substrate not covered by the hard mask layer to form a high aspect ratio shallow trench in the semiconductor substrate; forming an oxide liner on the bottom and sidewall of the high aspect ratio shallow trench; performing a LPCVD to form a first oxide layer to fill the high aspect ratio shallow trench, a void being formed in the first oxide layer; etching a portion of the first oxide layer to a certain depth of the high aspect ratio shallow trench and to expose the void; and performing a HDPCVD to form a second oxide layer to fill the high aspect ratio shallow trench.

Abstract: A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.

Abstract: A method for forming bottle-shaped trenches. First, a substrate is provided. Next, a hard mask with openings is formed on the substrate. The substrate is etched through the openings to form trenches with an upper portion and a lower portion. An isolated layer is formed conformally on the hard mask and in the trenches. A shield layer is formed in the lower portion of the trenches. A part of the insulating layer, which is not covered by the shield layer, is then removed. A protective layer is formed on the upper portion of the trenches. The shield layer and the isolated layer are removed. Finally, the substrate of the lower part of the trenches is wet etched using the protective layer as a mask so as to form bottle-shaped trenches.

Abstract: A method for forming bottle-shaped trenches. First, a substrate is provided. Next, a hard mask with openings is formed on the substrate. The substrate is etched through the openings to form trenches with an upper portion and a lower portion. An isolated layer is formed conformally on the hard mask and in the trenches. A shield layer is formed in the lower portion of the trenches. A part of the insulating layer, which is not covered by the shield layer, is then removed. A protective layer is formed on the upper portion of the trenches. The shield layer and the isolated layer are removed. Finally, the substrate of the lower part of the trenches is wet etched using the protective layer as a mask so as to form bottle-shaped trenches.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

Abstract: A manufacturing method for a shallow trench isolation region with high aspect ratio. The method comprises the steps of providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench by spray type etching, and forming a second insulation layer on the first insulation layer by low pressure CVD to fill the trench. According to the present invention, a void-free shallow trench isolation with high aspect ration can be achieved.

Abstract: A process of forming a bottle-shaped trench. A semiconductor substrate with a trench is provided, on which a pad layer and hard mask layer are sequentially formed. A dielectric layer is formed on the hard mask layer to fill the trench. Part of the dielectric layer is etched to expose the sidewall of the upper portion of the trench. A spacer is formed on the sidewall. The residual dielectric layer in the trench is removed, and the partial trench not covered by the spacer is etched to a bottle shape.

Abstract: A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.