SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF
A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.
1. Field of the Invention
The present invention relates to a single-sided access device for DRAM applications. More particularly, the present invention relates to a single-sided multi-finger gate fin field-effect-transistor (FinFET) or single-gate FinFET with improved device control and access drive current, and a method for making the same.
2. Description of the Prior Art
As known in the art, dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAM is arranged in a square array of one capacitor and transistor per cell. The transistor, which acts as switching device, comprises a gate and a silicon channel region underneath the gate. The silicon channel region is located between a pair of source/drain regions in a semiconductor substrate and the gate is configured to electrically connect the source/drain regions to one another through the silicon channel region.
A vertical double-gate fin field-effect-transistor (FinFET) has been developed for the next-generation 4F2 DRAM cell (F stands for minimum lithographic feature width). However, difficulties are frequently encountered in attempting to produce the vast arrays of vertical double-gate FinFET devices desired for semiconductor DRAM applications while maintaining suitable performance characteristics of the devices. For example, recently DRAM manufacturers face a tremendous challenge on shrinking the memory cell area as the word line spacing, i.e., the spacing between two adjacent word lines, continues to shrink. For high-speed DRAM applications, electrical coupling effect may be a problem as the spacing between two closely arranged word lines continues to shrink. Further, it is desired to provide an improved FinFET access device with higher gate current and therefore better device performance.
In light of the above, there is a strong need in this industry to provide a novel FinFET structure and the fabrication process thereof in order to avoid the aforesaid problems.
SUMMARY OF THE INVENTIONTo address these and other objects and in view of its purposes, the present invention provides a single-sided access device including an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
DETAILED DESCRIPTIONIn the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations and process steps are not disclosed in detail.
Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the figures. Also, in which multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration and description thereof, like or similar features will ordinarily be described with like reference numerals.
The term “horizontal” as used herein is defined as a plane parallel to the conventional major plane or primary surface of the semiconductor substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, if used, are defined with respect to the horizontal plane.
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Subsequently, a line-shaped recessed trench 22 is formed in the semiconductor substrate 10 between two adjacent STI trenches 21. The recessed trench 22 also extends along the reference x-axis direction between two STI trenches 21 to thereby define two active areas 10a and 10b. The recessed trench 22 may have a depth of about 150 nm, which is shallower than the STI trenches 21. An insulation region 18 such as silicon oxide is then formed in the recessed trench 22. Thereafter, the entire surface of the semiconductor substrate 10 is subjected to polishing process such as chemical mechanical process. As specifically indicated in
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Thereafter, a lining layer (not shown) may be formed on the interior surface of the line-shaped trenches 23, including the sidewall and bottom surface of the line-shaped trenches 23. According to the embodiment of the invention, the lining layer may comprise silicon oxide, silicon nitride, composite of silicon oxide and silicon nitride, or any other materials. Subsequently, an SOD gap-filler (not shown) is coated on the semiconductor substrate 10 and fills up the line-shaped trenches 23. The SOD gap filler may comprise polysilazane precursor but not limited thereto. A curing or densification process may be carried out to transform the SOD gap filler into silicon oxide gap filler. For example, the curing process may be carried out at high temperatures (e.g. 800-1000° C.) with the presence of steam. A CMP process may be carried out to remove the excess silicon oxide gap filler outside the line-shaped trenches 23, thereby forming STI regions 17. At this point, the STI regions 17 are coplanar with the top surface of the sacrificial layer 117.
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims
1. A single-sided access device, comprising:
- an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region disposed therebetween;
- a first trench isolation structure disposed at one side of the active fin structure, wherein the first trench isolation structure intersects with the isolation region;
- a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the first trench isolation structure so that the active fin structure is sandwiched by the first trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and
- a gate dielectric layer between the sidewall gate and the active fin structure.
2. The single-sided access device according to claim 1 wherein the active fin structure is tuning-fork shaped.
3. The single-sided access device according to claim 1 wherein the sidewall gate comprises a first finger that is situated directly under the isolation region.
4. The single-sided access device according to claim 3 wherein the first finger is in direct contact with the first trench isolation structure.
5. The single-sided access device according to claim 1 further comprising a second trench isolation structure that extends along a direction perpendicular to the first trench isolation structure.
6. The single-sided access device according to claim 5 wherein the sidewall gate comprises a second finger that is directly above the second trench isolation structure.
7. The single-sided access device according to claim 1 wherein the sidewall gate comprises TiN.
Type: Application
Filed: Sep 22, 2011
Publication Date: Mar 28, 2013
Inventors: Hsin-Jung Ho (New Taipei City), Jeng-Ping Lin (Taoyuan County), Neng-Tai Shih (Taipei City), Chang-Rong Wu (New Taipei City), Chiang-Hung Lin (New Taipei City), Chih-Huang Wu (Taoyuan County)
Application Number: 13/239,389
International Classification: H01L 29/78 (20060101);