Abstract: An IC structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the IC structure forming a first semiconductor fin and a second semiconductor fin protruding from a substrate, forming a high-k metal gate (HKMG) structure over the first semiconductor fin and the second semiconductor fin, forming a trench to separate the HKMG structure into two portions, conformally depositing a first dielectric layer in the trench, depositing a second dielectric layer over the first dielectric layer to fill the trench, wherein the second dielectric layer includes nitrogen, and the first dielectric layer is free of nitrogen, and planarizing the first dielectric layer and second dielectric layer to form a gate isolation structure in the trench.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming first fin structures and a second fin structures over a substrate, forming a first gate stack and a second gate stack that extend in a first direction across the first fin structures and the second fin structures, respectively, and etching the first gate stack and the second gate stack to form a first trench through the first gate stack and a second trench through the second gate stack. A first dimension of the first trench in the first direction is greater than a second dimension of the second trench in the first direction. The method further includes forming a first gate cutting structure and a second gate cutting structure in the first trench and the second trench, respectively.

Abstract: A computing system implementing a raw data filtering tool can aggregate multiple wafer images depicting a portion of an electronic device into a reference image, detect one or more of the wafer images have defects based on a comparison of the reference image to the wafer images, and generate a gauge file to include a set of the wafer images selected based on the detection of defects in the wafer images. The raw data filtering tool also can iteratively build defect maps that include differences between the reference image and the wafer images, and characterize the detected defect in the wafer images with a size and a location based on the defect maps. The raw data filtering tool can provide feedback to a foundry about wafer images were excluded from the set of the wafer images based on the detection of defects in the wafer images.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: This application discloses a computing system to obtain a wafer image of an electronic device having physical structures manufactured using one or more lithographic masks associated with a layout design describing the electronic design. The computing system can implement an unsupervised deep learning algorithm to process the wafer image to remove at least some noise from the wafer image, which generates a denoised wafer image. The computing system can extract contours corresponding to the physical structures of the electronic device from the denoised wafer image of the electronic device without use of the layout design or a mask design. The computing system can calibrate the layout design or the mask design describing the one or more lithographic masks based, at least in part, on the contours extracted from the denoised wafer image.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A method for driving a display panel having plural pixel electrodes arranged in rows and columns is provided. The method includes: receiving display data in plural periods; converting the received display data into a source voltage signal for each of the pixel electrodes; and applying the respective source voltage signal to each of the pixel electrodes. Each of the periods includes plural frames consisting of plural non-skipped frames and at least one skip frame subsequent to the non-skipped frames. The polarity of the source voltage signal in the non-skipped frame directly preceding the skip frame of one period is opposite to the polarity of the source voltage signal in the non-skipped frame directly preceding the skip frame of subsequent period.

Abstract: A method for driving a display panel having plural pixel electrodes arranged in rows and columns is provided. The method includes: receiving display data in plural periods; converting the received display data into a source voltage signal for each of the pixel electrodes; and applying the respective source voltage signal to each of the pixel electrodes. Each of the periods includes plural frames consisting of plural non-skipped frames and at least one skip frame subsequent to the non-skipped frames. The polarity of the source voltage signal in the non-skipped frame directly preceding the skip frame of one period is opposite to the polarity of the source voltage signal in the non-skipped frame directly preceding the skip frame of subsequent period.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.

Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.

Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.

Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.

Abstract: The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.

Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.

Abstract: A method includes providing a semiconductor substrate, and performing an ion implantation process to a surface of the substrate. The ion implantation process includes intermittently applying an ion beam to the surface, and while applying the ion beam, applying a heating process with a heating temperature above a threshold level.