Patents by Inventor Hsing-Kuo Hsia
Hsing-Kuo Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230358950Abstract: A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Publication number: 20230350142Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: July 5, 2023Publication date: November 2, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 11796735Abstract: A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.Type: GrantFiled: January 19, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Patent number: 11747563Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.Type: GrantFiled: August 10, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
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Patent number: 11715728Abstract: A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.Type: GrantFiled: July 15, 2020Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Publication number: 20230221511Abstract: A semiconductor device includes a plurality of intermediate waveguides. The plurality of intermediate waveguides are vertically disposed on top of one another, and vertically adjacent ones of the plurality of intermediate waveguides are laterally offset from each other. When viewed from the top, each of the plurality of intermediate waveguides essentially consists of a first portion and a second portion, the first portion has a first varying width that increases from a first end of the corresponding intermediate waveguide to a middle of the corresponding intermediate waveguide, and the second portion has a second varying width that decreases from the middle of the corresponding intermediate waveguide to a second end of the corresponding intermediate waveguide.Type: ApplicationFiled: May 26, 2022Publication date: July 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Tse Tang, Chewn-Pu Jou, Chih-Wei Tseng, Hsing-Kuo Hsia, Ming Yang Chung
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Publication number: 20230215853Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
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Publication number: 20230215854Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Chen-Hua Yu, Jiun Yi Wu, Hsing-Kuo Hsia
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Publication number: 20230161120Abstract: A semiconductor package includes a first interposer having a first substrate, a first redistribution structure over a first side of the first substrate, and a first waveguide over the first redistribution structure and proximate to a first side of the first interposer, where the first redistribution structure is between the first substrate and the first waveguide. The semiconductor package further includes a photonic package attached to the first side of the first interposer, where the photonic package includes: an electronic die, and a photonic die having a plurality of dielectric layers and a second waveguide in one of the plurality of dielectric layers, where a first side of the photonic die is attached to the electronic die, and an opposing second side of the photonic die is attached to the first side of the first interposer, where the second waveguide is proximate to the second side of the photonic die.Type: ApplicationFiled: March 24, 2022Publication date: May 25, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Patent number: 11605621Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.Type: GrantFiled: December 14, 2020Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Jiun Yi Wu, Hsing-Kuo Hsia
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Patent number: 11605622Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.Type: GrantFiled: June 13, 2022Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
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Patent number: 11592618Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.Type: GrantFiled: April 9, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
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Publication number: 20230014813Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20230012157Abstract: A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.Type: ApplicationFiled: January 19, 2022Publication date: January 12, 2023Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Publication number: 20220404552Abstract: A device includes a dielectric layer, a plurality of grating structures, and a dielectric material between the plurality of grating structures and on top of the plurality of grating structures. The grating structures are arranged on the dielectric layer and separated from each other, the plurality of grating structures each having a bottom portion and top portion, the top portion having a first width and the bottom portion having a second width, the second width being larger than the first width.Type: ApplicationFiled: September 1, 2021Publication date: December 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Wei KUO, Chewn-Pu JOU, Hsing-Kuo Hsia
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Publication number: 20220392881Abstract: A package includes an interposer structure including a first via; a first interconnect device including conductive routing and which is free of active devices; an encapsulant surrounding the first via and the first interconnect device; and a first interconnect structure over the encapsulant and connected to the first via and the first interconnect device; a first semiconductor die bonded to the first interconnect structure and electrically connected to the first interconnect device; and a first photonic package bonded to the first interconnect structure and electrically connected to the first semiconductor die through the first interconnect device, wherein the first photonic package includes a photonic routing structure including a waveguide on a substrate; a second interconnect structure over the photonic routing structure, the second interconnect structure including conductive features and dielectric layers; and an electronic die bonded to and electrically connected to the second interconnect structure.Type: ApplicationFiled: August 10, 2022Publication date: December 8, 2022Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Publication number: 20220382003Abstract: A device includes a photonic routing structure including a silicon waveguide, photonic devices, and a grating coupler, wherein the silicon waveguide is optically coupled to the photonic devices and to the grating coupler; an interconnect structure on the photonic routing structure, wherein the grating coupler is configured to optically couple to an external optical fiber disposed over the interconnect structure; and computing sites on the interconnect structure, wherein each computing site includes an electronic die bonded to the interconnect structure, wherein each electronic die of the computing sites is electrically connected to a corresponding photonic device of the photonic devices.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Chen-Hua Yu, Hsing-Kuo Hsia
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Publication number: 20220381985Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.Type: ApplicationFiled: August 10, 2022Publication date: December 1, 2022Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
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Publication number: 20220365278Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 11493689Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.Type: GrantFiled: July 16, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu