Patents by Inventor Hsing-Kuo Hsia
Hsing-Kuo Hsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10930628Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.Type: GrantFiled: June 11, 2019Date of Patent: February 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
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Publication number: 20210018678Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.Type: ApplicationFiled: August 17, 2020Publication date: January 21, 2021Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Pin-Tso Lin, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20200395347Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.Type: ApplicationFiled: June 14, 2019Publication date: December 17, 2020Inventors: Chen-Hua Yu, Jiun Yi Wu, Hsing-Kuo Hsia
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Publication number: 20200395302Abstract: In an embodiment, a device includes: a first and second integrated circuit die; and a hybrid redistribution structure including: a first photonic die; a second photonic die; a first dielectric layer laterally surrounding the first photonic die and the second photonic die, the first integrated circuit die and the second integrated circuit die being disposed adjacent a first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a major surface of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; a second dielectric layer disposed adjacent a second side of the first dielectric layer; and a waveguide disposed between the first dielectric layer and the second dielectric layer, the waveguide optically coupling the first and second photonic dies.Type: ApplicationFiled: June 14, 2019Publication date: December 17, 2020Inventors: Chen-Hua Yu, Jiun Yi Wu, Hsing-Kuo Hsia
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Patent number: 10867982Abstract: An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.Type: GrantFiled: June 14, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Jiun Yi Wu, Hsing-Kuo Hsia
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Patent number: 10866373Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: GrantFiled: June 25, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20200286845Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.Type: ApplicationFiled: May 20, 2020Publication date: September 10, 2020Inventors: CHUEI-TANG WANG, CHIH-CHIEH CHANG, YU-KUANG LIAO, HSING-KUO HSIA, CHIH-YUAN CHANG, JENG-SHIEN HSIEH, CHEN-HUA YU
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Patent number: 10746923Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.Type: GrantFiled: June 24, 2019Date of Patent: August 18, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Pin-Tso Lin, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Patent number: 10665560Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.Type: GrantFiled: October 27, 2017Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chuei-Tang Wang, Chih-Chieh Chang, Yu-Kuang Liao, Hsing-Kuo Hsia, Chih-Yuan Chang, Jeng-Shien Hsieh, Chen-Hua Yu
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Publication number: 20200088960Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.Type: ApplicationFiled: November 18, 2019Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuei-Tang Wang, Jeng-Shien Hsieh, Hsing-Kuo Hsia, Chen-Hua Yu
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Publication number: 20200003975Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.Type: ApplicationFiled: June 25, 2019Publication date: January 2, 2020Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Sung-Hui Huang, Kuan-Yu Huang, Kuo-Chiang Ting, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20200003950Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.Type: ApplicationFiled: June 24, 2019Publication date: January 2, 2020Inventors: Chen-Hua Yu, Hsing-Kuo Hsia, Kuo-Chiang Ting, Pin-Tso Lin, Sung-Hui Huang, Shang-Yun Hou, Chi-Hsi Wu
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Publication number: 20200006304Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove.Type: ApplicationFiled: June 11, 2019Publication date: January 2, 2020Inventors: Chih-Chieh Chang, Chung-Hao Tsai, Chuei-Tang Wang, Hsing-Kuo Hsia, Chen-Hua Yu
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Patent number: 10481351Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.Type: GrantFiled: December 19, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuei-Tang Wang, Jeng-Shien Hsieh, Hsing-Kuo Hsia, Chen-Hua Yu
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Patent number: 10371893Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.Type: GrantFiled: January 31, 2018Date of Patent: August 6, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chuei-Tang Wang, Hsing-Kuo Hsia, Yu-Kuang Liao, Chih-Chieh Chang
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Publication number: 20190237454Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.Type: ApplicationFiled: August 1, 2018Publication date: August 1, 2019Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20190162901Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.Type: ApplicationFiled: January 31, 2018Publication date: May 30, 2019Inventors: Chen-Hua Yu, Chuei-Tang Wang, Hsing-Kuo Hsia, Yu-Kuang Liao, Chih-Chieh Chang
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Publication number: 20190146166Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.Type: ApplicationFiled: December 19, 2018Publication date: May 16, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuei-Tang Wang, Jeng-Shien Hsieh, Hsing-Kuo Hsia, Chen-Hua Yu
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Publication number: 20190131267Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Inventors: CHUEI-TANG WANG, CHIH-CHIEH CHANG, YU-KUANG LIAO, HSING-KUO HSIA, CHIH-YUAN CHANG, JENG-SHIEN HSIEH, CHEN-HUA YU
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Patent number: 10267990Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.Type: GrantFiled: November 30, 2018Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chuei-Tang Wang, Hsing-Kuo Hsia, Yu-Kuang Liao, Chih-Chieh Chang