Patents by Inventor Hsingya Arthur Wang
Hsingya Arthur Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040152260Abstract: The present invention provides non-volatile memory cell transistors that have increased control-to-floating gate coupling coefficients due to a non-uniform gate surface area. In memory cells of the present invention, the floating gate is formed with a non-flat, non-uniform surface, which significantly increases the surface area interface between the floating gate and the inter-gate dielectric as well as the surface area interface between the inter-gate dielectric and the control gate. As a result, the inter-gate capacitance and the gate coupling coefficient are significantly increased. A high gate coupling coefficient allows the creation of small sized high performance memory cells that have high program and erase efficiency and read speed and can function at lower operation voltages. Higher gate coupling ratio allows also lowering operation voltages of memory cell which simplifies flash chip design, especially for lower power supply voltages.Type: ApplicationFiled: September 7, 2001Publication date: August 5, 2004Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Patent number: 6746906Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.Type: GrantFiled: March 13, 2001Date of Patent: June 8, 2004Assignee: Hynix Semiconductor, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20030218206Abstract: A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.Type: ApplicationFiled: May 6, 2003Publication date: November 27, 2003Applicant: Hynix Semiconductor Inc.Inventors: Hsingya Arthur Wang, Kai-Cheng Chou, Peter Rabkin
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Publication number: 20030203571Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.Type: ApplicationFiled: March 19, 2003Publication date: October 30, 2003Applicant: Hynix Semiconductor America, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20030102503Abstract: In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.Type: ApplicationFiled: November 26, 2001Publication date: June 5, 2003Applicant: Hynix Semiconductor, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Patent number: 6559008Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.Type: GrantFiled: October 4, 2001Date of Patent: May 6, 2003Assignee: Hynix Semiconductor America, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20030068860Abstract: Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.Type: ApplicationFiled: October 4, 2001Publication date: April 10, 2003Applicant: Hynix Semiconductor America, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20030032239Abstract: Structures and methods for flash memory transistors are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer(s) are deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide layer/spacer may be formed on the etch resistant layer to control the resulting transistor junction configuration. As a result within the same process various transistors may be formed satisfying various requirements. Contact holes to the drain and source regions of the memory and peripheral transistors are then formed. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers. The spacing between the drain/source contacts and the gate layers can be greatly reduced increasing the density of the memory array transistors and reducing chip size.Type: ApplicationFiled: August 10, 2001Publication date: February 13, 2003Applicant: Hynix Semiconductor America, Inc.Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Patent number: 6509237Abstract: An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source junction. The common diffusion step is accomplished while an oxide spacer is present over a gate stack, prior to the common diffusion step, resulting in faster source diffusion and a graded source junction, while the slower diffusion in the drain region results in an abrupt drain junction. The oxide spacer moves the drain junction further away from the gate stack to allow for greater cell densities.Type: GrantFiled: May 11, 2001Date of Patent: January 21, 2003Assignee: Hynix Semiconductor America, Inc.Inventors: Hsingya Arthur Wang, Peter Rabkin, Frank Qian
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Publication number: 20020168824Abstract: An abrupt drain junction and a graded source junction are fabricated using a common diffusion step, wherein the common diffusion step is used to create both the drain junction-and the source junction. The common diffusion step is accomplished while an oxide spacer is present over a gate stack, prior to the common diffusion step, resulting in faster source diffusion and a graded source junction, while the slower diffusion in the drain region results in an abrupt drain junction. The oxide spacer moves the drain junction further away from the gate stack to allow for greater cell densities.Type: ApplicationFiled: May 11, 2001Publication date: November 14, 2002Inventors: Hsingya Arthur Wang, Peter Rabkin, Frank Qian
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Publication number: 20020123182Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.Type: ApplicationFiled: March 13, 2001Publication date: September 5, 2002Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20020123180Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.Type: ApplicationFiled: March 1, 2001Publication date: September 5, 2002Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou
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Publication number: 20020105036Abstract: A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.Type: ApplicationFiled: February 2, 2001Publication date: August 8, 2002Inventors: Hsingya Arthur Wang, Yuan Tang, Haike Dong, Ming Sang Kwan, Peter Rabkin
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Publication number: 20020048192Abstract: A structure for a flash memory cell is described in which a triple well is formed with the memory cell residing in a P-well, which in turn is deposed in an N-well in a P-type substrate. The structure provides the ability to operate such memories with considerably lower operating potentials than prior art devices. A process for fabricating the flash memory cell is also described.Type: ApplicationFiled: October 12, 2001Publication date: April 25, 2002Inventors: Hsingya Arthur Wang, Jein-Chen Young, Ming-Sang Kwan
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Patent number: 6169693Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.Type: GrantFiled: October 28, 1999Date of Patent: January 2, 2001Assignee: Hyundai Electronics America, Inc.Inventors: I-Chuin Peter Chan, Feng Frank Qian, Hsingya Arthur Wang
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Patent number: 6043123Abstract: A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.Type: GrantFiled: May 27, 1997Date of Patent: March 28, 2000Assignee: Hyundai Electronics America, Inc.Inventors: Hsingya Arthur Wang, Jein-Chen Young, Ming-Sang Kwan
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Patent number: 6026026Abstract: An erase method provides for self-converging erase on a flash memory cell by rapidly switching a bias on a control gate while a lateral field is present in a channel region. Preferably, the lateral field is provided by differentially biasing the source and drain of the cell and the change in bias of the control gate is sufficiently fast to induce a transient response at the floating gate. The net transient vertical field formed across a tunneling oxide between the channel region and the floating gate causes moderate hot carrier injection between the channel region and the floating gate. This method is self-converging, since carrier injection to the floating gate will not happen unless a sufficient number of carriers are removed from the floating gate during the array step. Since the bulk of the self-converging effect occurs as the control gate voltage is transitioning and shortly thereafter, very little time is needed at the end of an erase pulse to effect this response.Type: GrantFiled: December 5, 1997Date of Patent: February 15, 2000Assignee: Hyundai Electronics America, Inc.Inventors: I-Chuin Peter Chan, Feng Frank Qian, Hsingya Arthur Wang
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Patent number: 5989938Abstract: The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.Type: GrantFiled: September 4, 1997Date of Patent: November 23, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Hsingya Arthur Wang, Bandali B. Mohamed, Shyam Garg, Bruce Pickelsimer
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Patent number: 5981364Abstract: Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.Type: GrantFiled: December 6, 1995Date of Patent: November 9, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Mark T. Ramsbey, Hsingya Arthur Wang, Yu Sun
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Patent number: 5920506Abstract: Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.Type: GrantFiled: September 26, 1997Date of Patent: July 6, 1999Assignee: Hyundai Electronics America, Inc.Inventors: Hsingya Arthur Wang, Haike Dong, Jein-Chen Young, Yuan Tang, Aaron Yip, Kenneth Miu