Abstract: Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit.

Abstract: After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.

Abstract: A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to the field oxide layer and then etching back the planarizing layer and field oxide layer to a desired thickness.

Abstract: A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.

Abstract: A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.

Abstract: An E.sup.2 PROM device includes a semiconductor body having source and drain regions and a channel region, with a gate oxide over the channel region and a floating gate over the gate oxide. An oxide isolation region contains a doped polysilicon erase gate, so that erasing of the device takes place by electron flow from the floating gate to the erase gate through a thin oxide portion of the oxide isolation region, at a position spaced from the gate oxide. The inclusion of the erase gate in the oxide isolation region results in smaller overall device size than previously achieved.

Abstract: A simplified fabrication procedure for making flash EEPROM memory cells is disclosed. The method comprises performing a double-diffuse (deep) junction implant after the shallow source/drain of the memory cell have been implanted and formed. A high energy double-diffuse implant is used to replace separate, individual implant and diffusion steps which results in a memory cell having, less damage to its substrate.

Abstract: A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.

Abstract: In a semiconductor device, a layer of nitrogen doped polysilicon is applied to a gate oxide in turn provided on a semiconductor body, and then a silicide film is applied to the polysilicon layer. The nitrogen in the polysilicon layer inhibits growth of native oxide on the polysilicon layer prior to the application of silicide, and at subsequent high temperature processing steps, so that the problem of the silicide layer lifting from the polysilicon layer due to this native oxide growth is avoided during subsequent high temperature processing of the device.

Abstract: The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.

Abstract: A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.