Abstract: A method for manufacturing a bit line. A substrate having a dielectric layer on the substrate and a contact hole penetrating through the dielectric layer and exposing portions of the substrate is provided. A patterned conductive layer is formed on the dielectric layer and fills the contact hole. The surface of the patterned conductive layer is converted into an oxide layer. The oxide layer is removed. A silicide layer is formed on the patterned conductive layer.

Abstract: A method for forming the lower electrode of a capacitor comprising the steps of forming a first dielectric layer, a silicon nitride layer and an oxide layer over a substrate. Then, a first conducting layer is formed in an opening making electrical contact with a specified region of the substrate. Next, a first hemispherical grained silicon layer and a second dielectric layer are formed over the first conductive layer. Thereafter, the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer are patterned. Subsequently, a second conductive layer and a second hemispherical grained silicon layer are formed over the whole substrate structure. Next, portions of the second hemispherical grained silicon layer and the second conductive layer lying above the oxide layer and the second dielectric layer are removed. Finally, the second dielectric layer is removed to expose the first hemispherical grained silicon layer.

Abstract: A method for manufacturing a metal-oxide-semiconductor (MOS) transistor is described. In the invention, doped regions of the local pocket type are formed in the substrate after the source/drain terminals of a MOS transistor in the logic circuit area are formed. The method includes the steps of forming an insulation layer over the entire substrate. Then, a portion of the insulation layer is removed to expose the spacers on the sidewalls of the gate electrode. Subsequently, the spacers are removed, and then an ion implantation operation is conducted to implant dopants into the substrate through the windows formed by the uprooted spacers. Ultimately, doped regions of the local pocket type are formed in the substrate under the lightly doped drain source/drain terminals of a MOS transistor.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer on a semiconductor substrate, and forming an oxidation masking layer on the pad layer, wherein the pad layer relieves stress from the oxidation masking layer. Next, portions of the oxidation masking layer and the pad layer are patterned and etched. A first oxide layer is thermally grown on the substrate, and a second oxide spacer is formed on a sidewall of the pad layer and the oxidation masking layer. After forming a nitride spacer on a surface of the second oxide spacer, the substrate is thermally oxidized to form the isolation region in the substrate.

Abstract: The capacitor for a DRAM is formed to have a textured bottom electrode using wet etch processes. A planarized dielectric layer is formed over the transfer FETs and bit line of a capacitor over bit line DRAM cell. A layer of silicon nitride is deposited over the planarized dielectric layer. A layer of silicon oxide is deposited over the silicon nitride layer and then a contact via is etched to expose the charge storage node of a transfer FET of the DRAM cell. A layer of polysilicon is deposited over the silicon oxide layer and into the contact via to connect the polysilicon layer to the charge storage node of the transfer FET. The polysilicon layer is patterned to define bottom capacitor plates. The silicon oxide layer is etched using hydrofluoric acid to expose the bottom surface of the polysilicon bottom capacitor plate. Next, a hydrofluoric acid dip is used to create a rugged polysilicon surface on the upper and lower surfaces of the bottom capacitor electrodes.

Abstract: A method of forming a bit line of a dynamic random access memory. An insulating layer is used to cover the source/drain region in a substrate. A trench is formed in the insulating layer above the source/drain region. Then, a portion of the insulating layer inside the trench is removed to form an opening which exposes the source/drain region. A conductor is used to fill the trench and the opening so as to form a bit line and a metal plug, respectively.

Abstract: A supplementary implantation method for fabricating a twin gate CMOS. A first conductivity-type well region and a second conductivity-type well region, with an isolating region therebetween, are formed on a semiconductor substrate. A gate oxide layer is formed on the surface of the first and second conductivity-type well regions. Next, a polysilicon layer is formed on the surface of the gate oxide layer and is lightly doped with ions of a first conductivity-type. Ions of a second conductivity-type are then implanted in the polysilicon layer above the first conductivity-type well region and thereby convert the layer into a lightly doped layer of the second conductivity-type, while leaving the polysilicon layer above the second conductivity-type well region still lightly doped with the first conductivity-type ions.