Abstract: A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

Abstract: A method and a measuring apparatus for measuring noise of a device under test (DUT) is provided, wherein the DUT is connected to a link partner (LP) device via a cable, and the measuring apparatus is coupled to the DUT and LP device. The method includes: controlling the LP device to transmit a far-end data sequence to the DUT according to transmission data; controlling the DUT to recover the transmission data for generating aided-data sequence according to the transmission data, wherein the aided-data sequence is configured to perform cancellation with a received far-end data sequence to generate a cancellation result; generating a first noise value and a second noise value in a first training phase and a second training phase, respectively; and estimating noise from at least one circuit according to the first noise value and the second noise value.

Abstract: A transceiver circuit includes an ADC and an echo-cancellation circuit, wherein the echo-cancellation circuit includes a steady circuit, a transient circuit and an output circuit. In the operations of the transceiver circuit, the ADC is configured to perform an analog-to-digital conversion operation on an analog input signal to generate a digital input signal. The steady circuit is configured to generate a steady echo response according to a transmitting signal. The transient circuit is configured to generate an echo response adjustment signal according to a phase change of a clock signal used by the transmitting signal. The output circuit is configured to generate an output signal according to the digital input signal, the steady echo response, and the echo response adjustment signal.

Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Abstract: An echo cancelling system includes a data transmitter circuit and an echo canceller circuit. The data transmitter circuit is configured to receive a first transmitted signal. The first transmitted signal has a first sampling rate. The echo canceller circuit is configured to generate a second transmitted signal according to the first transmitted signal. The second transmitted signal has a second sampling rate. The second sampling rate is greater than the first sampling rate. The echo canceller circuit is further configured to generate an echo cancelling signal according to the second transmitted signal. The data transmitter circuit is further configured to generate an output signal according to a received signal and the echo cancelling signal.

Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Abstract: A transceiver circuit includes an ADC and an echo-cancellation circuit, wherein the echo-cancellation circuit includes a steady circuit, a transient circuit and an output circuit. In the operations of the transceiver circuit, the ADC is configured to perform an analog-to-digital conversion operation on an analog input signal to generate a digital input signal. The steady circuit is configured to generate a steady echo response according to a transmitting signal. The transient circuit is configured to generate an echo response adjustment signal according to a phase change of a clock signal used by the transmitting signal. The output circuit is configured to generate an output signal according to the digital input signal, the steady echo response, and the echo response adjustment signal.

Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Abstract: This invention discloses a signal receiving device for Ethernet and a control method thereof. The signal receiving device includes a gain control circuit, an alien near-end crosstalk canceller, a noise canceller, and a DFE. The gain control circuit adjusts an input signal of the signal receiving device according to a setting parameter. The alien near-end crosstalk canceller cancels an alien near-end crosstalk interference. The noise canceller uses a first filter to cancel noises. The DFE uses a second filter to cancel an inter-symbol interference of the input signal. The method includes steps of: temporarily stopping the gain control circuit from updating the setting parameter before a seed collision occurs, and temporarily stopping one of the noise canceller and the decision feedback canceller from updating the first filter coefficient of the first filter or the second filter coefficient of the second filter temporarily during the seed collision.

Abstract: A three-way handshaking method includes: controlling a first port in a first specific mode to send a first specific signal to a second port, and controlling the first port to enter a second specific mode; when the first port receives a second specific signal, determining the second port is in the second specific mode and controlling the first port to send a third specific signal to the second port; and when it is determined that the second port is in a third specific mode, controlling the first port to enter the third specific mode.

Abstract: A united power module having an external input and a first input is provided. The united power module includes a load block, a protection circuitry and a detection block. The detection block includes an analog circuitry. The load block and an end of the protection circuitry are electrically coupled to the external input. The load block, the first input, and another end of the protection circuitry are electrically coupled to the detection block. The load block is supplied by an external power received from the external input. The protection circuitry receives the external power and outputs an auxiliary power. The analog circuitry receives a first power from the first input under a normal power supply state, or receives the auxiliary power under an auxiliary power supply state.

Abstract: A control method applied to an Operating-Mode Finite-State-Machine (OPFSM) arranged for deciding a behavior of a first port of an apparatus includes: controlling the OPFSM to enter a second local state from a first local state and controlling the first port to send a signal with a wakeup pattern to a link partner of the first port when the state of the OPFSM is the first local state, and a wakeup request bit is a first local value.

Abstract: A signal transmission method is provided. The method includes the following steps. First, an output signal filtered from a square wave signal by a high pass filter is received. Then, the output signal is sampled at each time interval, so as to generate the sampled values. Next, the sampled values are compared with at least one threshold to generate comparison results. Finally, a signal pattern corresponding to the output signal is identified according to the comparison results.

Abstract: This disclosure provides a network apparatus with communication ports, each connected to multiple channels, assigned a seed for eliminating the interference among the communication ports, and operable in a master or slave mode, each channel having a communication unit which comprises: an echo canceller, a near-end crosstalk (NEXT) canceller, a decision feedback equalizer, and a control unit configured for controlling the communication ports if the echo canceller and the decision feedback equalizer keep updating their filter coefficients according to the same symbol during a first pre-determined time-interval; wherein when more than two of the communication ports operate in the master mode, the control unit assigns different seeds to the more than two communication ports; and wherein when successive two of the communication ports operate in the slave mode, the control unit stops either the echo canceller or the NEXT canceller from updating their filter coefficients during a second pre-determined time-interval.

Abstract: A master-slave detection method includes: every single time period, utilizing a random manner for determining whether a first device is used to transmit a specific pulse signal to a second device; every single time period, utilizing a random manner for determining whether the second device is used to transmit the specific pulse signal to the first device; when the first device receives at least one portion of the specific pulse signal earlier than the second device, setting the first device as a master device, stopping the master device from sending the specific pulse signal and utilizing the master device to start transmitting a specific sequence; and setting the second device as a slave device when the second device receives the specific sequence. The at least one portion of the specific pulse signal includes continuous single pulses.

Abstract: An impedance adjustment method for a communication device, wherein the communication device has a plurality of impedance paths for selection, includes: selecting an initial impedance path; and utilizing a predetermined algorithm to examine a portion of the plurality of impedance paths by starting from the initial impedance path for selecting an optimized impedance path for the communication device. A delay capacitance adjustment method for a communication device, wherein the communication device has a plurality of delay capacitance paths for selection, includes: selecting an initial delay capacitance path; and utilizing a predetermined algorithm to examine a portion of the plurality of delay capacitance paths by starting from the initial delay capacitance path for selecting an optimized delay capacitance path of the communication device.

Abstract: A signal transmission method is provided. The method includes the following steps. First, an output signal filtered from a square wave signal by a high pass filter is received. Then, the output signal is sampled at each time interval, so as to generate the sampled values. Next, the sampled values are compared with at least one threshold to generate comparison results. Finally, a signal pattern corresponding to the output signal is identified according to the comparison results.

Abstract: A united power module having an external input and a first input is provided. The united power module includes a load block, a protection circuitry and a detection block. The detection block includes an analog circuitry. The load block and an end of the protection circuitry are electrically coupled to the external input. The load block, the first input, and another end of the protection circuitry are electrically coupled to the detection block. The load block is supplied by an external power received from the external input. The protection circuitry receives the external power and outputs an auxiliary power. The analog circuitry receives a first power from the first input under a normal power supply state, or receives the auxiliary power under an auxiliary power supply state.

Abstract: A three-way handshaking method includes: controlling a first port in a first specific mode to send a first specific signal to a second port, and controlling the first port to enter a second specific mode; when the first port receives a second specific signal, determining the second port is in the second specific mode and controlling the first port to send a third specific signal to the second port; and when it is determined that the second port is in a third specific mode, controlling the first port to enter the third specific mode.