Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer is arranged between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based upon one or more voltages applied to the bottom electrode or the top electrode. A seed layer is arranged between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic crystal phase.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Abstract: Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.

Abstract: A method for estimating film thickness in CMP includes the following operations. A substrate with a film formed thereon is disposed over a polishing pad with a slurry dispensed between the film and the polishing pad. A CMP operation is performed to reduce a thickness of the film. An in-situ electrochemical impedance spectroscopy (EIS) measurement is performed during the CMP operation by an EIS device to estimate the thickness of the film real-time. The CMP operation is ended when the estimated thickness of the film obtained from the fit parameters of the first equivalent electrical circuit model reaches a target thickness.

Abstract: The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes and image sensor element disposed within a substrate. The substrate comprises a first material. The image sensor element includes an active layer comprising a second material different from the first material. A buffer layer is disposed between the active layer and the substrate. The buffer layer extends along outer sidewalls and a bottom surface of the active layer. A capping structure overlies the active layer. Outer sidewalls of the active layer are spaced laterally between outer sidewalls of the capping structure such that the capping structure continuously extends over outer edges of the active layer.

Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

Abstract: Each memory cell in an array includes a vertical stack that comprises a bottom electrode, a memory element, and a top electrode. An etch stop dielectric layer is formed over the array of memory cells. A first dielectric matrix layer is formed over the etch stop dielectric layer. The top surface of the first dielectric matrix layer is raised in a memory array region relative to a logic region due to topography. The first dielectric matrix layer is planarized by performing a chemical mechanical planarization process using top portions of the etch stop dielectric layer. A second dielectric matrix layer is formed over the first dielectric matrix layer. Metallic cell contact structures are formed through the second dielectric matrix layer on a respective subset of the top electrodes over vertically protruding portions of the etch stop dielectric layer that laterally surround the array of vertical stacks.

Abstract: The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.

Abstract: In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

Abstract: A pad conditioner for conditioning a polishing surface of a polishing pad includes a conditioning disk, a disk holder, and a disk arm. The conditioning disk includes a substrate plate and at least two abrasive segments. The conditioning disk includes at least one channel by which debris and spent slurry may be evacuated. The abrasive segments are on a surface of the substrate plate, and form at least one channel segment therebetween. Each channel segment extends from about the center of the surface to substantially the outer rim of the substrate plate. The disk holder to which the conditioning disk is mounted includes a through hole. The disk arm to which the conditioning disk is mounted includes an opening in fluid communication with the at least one channel segment via the through hole for evacuating the debris and spent slurry by a vacuum module.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.

Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) pad, and an associated method to perform a CMP process. In some embodiments, the CMP pad comprises a polishing layer having a front surface with protruding asperities while a back surface being planar. A film electrode is attached to the back surface of the polishing layer and is isolated from the front surface of the polishing layer. The CMP pad further comprises an insulating layer covering sidewall and bottom surfaces of the film electrode.

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.