Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include a substrate including a central portion and a pair of outer portions. A first self-assembled monolayer is attached to the central portion of the substrate. A second self-assembled monolayer is attached to the first self-assembled monolayer. A first dielectric layer is disposed on each of the outer portions. A second dielectric layer is disposed on the first dielectric layer.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.

Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.

Abstract: A sensor system can comprise a light source generating a light pulse that is collimated, and a plurality of optical elements. Each of the plurality of optical elements is configured to rotate independently about an axis that is substantially common, and the plurality of optical elements operate to collectively direct the light pulse to one or more objects in an angle of view of the sensor system. Furthermore, the sensor system can comprise a detector configured to receive, via the plurality of optical elements, at least a portion of photon energy of the light pulse that is reflected back from the one or more objects in the angle of view of the sensor system, and convert the received photon energy into at least one electrical signal.

Abstract: Hollow motor apparatuses and associated systems and methods for manufacturing hollow motor apparatuses may be provided. In one implementation, a hollow motor apparatus may include a rotor assembly rotatable about a rotation axis, a stator assembly positioned adjacent to, and coaxially with, the rotor assembly, and a bearing assembly configured to maintain a position of the rotor assembly relative to the stator assembly. The rotor assembly may include an inner portion disposed around an opening configured to receive and to rotate at least a portion of a payload. The bearing assembly may be disposed outside of the inner portion of the rotor assembly.

Abstract: Techniques for measuring defectivity using model-less scatterometry with cognitive machine learning are provided. In one aspect, a method for defectivity detection includes: capturing SEM images of defects from a plurality of training wafers; classifying type and density of the defects from the SEM images; making training scatterometry scans of a same location on the training wafers as the SEM images; training a machine learning model to correlate the training scatterometry scans with the type and density of the defects from the same location in the SEM images; making scatterometry scans of production wafers; and detecting defectivity in the production wafers by measuring the type and density of the defects in the production wafers using the machine learning model, as trained, and the scatterometry scans of the production wafers. A system for defectivity detection is also provided.

Abstract: A semiconductor interconnect structure and a method of fabricating the same are provided. The semiconductor interconnect structure includes a sea of interconnect lines including metal lines and neighboring dummy lines. The semiconductor interconnect structure further includes a dielectric layer arranged between the sea of lines.

Abstract: An electronic device with a fingerprint sensing function and a fingerprint image processing method are provided. The electronic device includes a processor, a fingerprint sensor, and a temperature sensor. The fingerprint sensor is coupled to the processor. The fingerprint sensor is configured to obtain a current fingerprint image. The temperature sensor is coupled to the processor. The temperature sensor is configured to obtain current temperature information. The processor obtains current background noise according to the current temperature information, and removes the background noise from the current fingerprint image to generate a corrected fingerprint image.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A method of forming a semiconductor device includes forming a dielectric spacer along sidewalls of a plurality of interconnect openings extending through a sacrificial dielectric layer and a first dielectric layer until a top portion of a first conductive material, the dielectric spacer includes a dielectric material having a dielectric constant higher than a dielectric constant of the sacrificial dielectric layer and higher than a dielectric constant of the first dielectric layer, conformally depositing a barrier liner within the plurality of interconnect openings above and in direct contact with the dielectric spacer, filling the interconnect openings with a second conductive material, removing the sacrificial dielectric layer to expose portions of the dielectric spacer above the first dielectric layer, and reducing a thickness of exposed portions of the dielectric spacer.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.

Abstract: A driving device includes two rotor assemblies, a stator assembly, and a positioning assembly. Each rotor assembly includes a rotation axis and a rotor. The rotor includes a hollow chamber. The two rotor assemblies include a first rotor assembly and a second rotor assembly, a rotation axis of the first rotor assembly is parallel with a rotation axis of the second rotor assembly, a rotor of the first rotor assembly is at least partially embedded in a chamber of a rotor of the second rotor assembly. The stator assembly is surroundingly disposed at an outer side of the two rotor assemblies and drives a rotor. The rotor driven by the stator assembly causes another rotor of one of the first rotor assembly and the second rotor assembly to rotate. The positioning assembly is located outside of the rotors, and limits the rotors to rotate around corresponding fixed rotation axes.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: Hollow motor apparatuses and associated systems and methods for manufacturing the same are disclosed herein. In representative embodiment, a hollow motor apparatus includes a rotor assembly rotatable about a rotation axis, a stator assembly positioned adjacent to the rotor assembly and coaxially with the rotor assembly relative to the rotation axis, and a bearing assembly operably coupled to the rotor assembly. The rotor assembly has an inner portion around an opening configured to receive at least a portion of a payload. The bearing assembly is disposed outside the inner portion of the rotor assembly and is configured to maintain a position of the rotor assembly relative to the stator assembly.

Abstract: A laser-based measurement device includes a motor comprising a hollow shaft. The laser-based measurement device also includes a laser transmitter disposed in the hollow shaft. The laser-based measurement device also includes an optical device disposed at the motor. The motor is configured to drive the optical device to rotate. The optical device is configured to guide a laser beam transmitted by the laser transmitter out of the hollow shaft, or to guide the laser beam reflected by an external environment into the hollow shaft.