Abstract: A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A laser-based measurement device includes a laser transmitter; a laser receiver; an optical device configured to guide a laser beam emitted by the laser transmitter out of the laser-based measurement device and guide the laser beam reflected by an external environment in the laser receiver; and a driving device including a first magnetic member connected to the optical device and a second magnetic member. The driving device is configured to drive the optical device to vibrate through interaction between the first magnetic member and the second magnetic member, to change a guiding direction of the laser beam passing through the optical device.

Abstract: A LiDAR system includes a light source to emit pulsed laser light beams, a scanning optical assembly to direct the pulsed laser light beams to scan an environment for detecting one or more objects therein, and a receiver to receive, via the scanning optical assembly, return light beams reflected by the one or more objects. The scanning optical assembly includes a first optical element rotatable about a first axis and to receive a light beam at a first surface thereof and refract the light beam by a second surface thereof at which the light beam exits the first optical element, and a second optical element spaced from the first optical element and rotatable about a second axis. The second optical element includes a reflective surface to reflect the light beam to the environment and a refractive surface to refract the light beam to the reflective surface.

Abstract: A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

Abstract: A semiconductor structure including a metal layer including a Vdd metal line, a Vss metal line, signal lines and a high-k dielectric between the Vdd and Vss metal lines, and a dielectric surrounding the signal lines. A semiconductor structure including a metal layer including a Vdd metal line, a Vss metal line, signal lines, and a high-k dielectric between the Vdd metal line and the Vss metal line, where a width between the Vdd metal line and the Vss metal line is less than a width between each of the signal lines. A method including forming a bulk metal layer on a structure, removing portions of the bulk metal layer, remaining portions of the bulk metal layer form metal lines, the metal lines include a Vdd metal line, a Vss metal line and signal lines, and forming a high-k dielectric between the Vdd metal line and the Vss metal line.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

Abstract: The present invention discloses a receptor inhibitor of formula (I), a pharmaceutical composition comprising the same and the use thereof.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

Abstract: An interconnect stack structure includes a first metal level of horizontal power line wiring; a second metal level of horizontal power line wiring; wherein the first metal level is not adjacent to the second metal level; two top-via structures comprising a first via and a second via, the two top-via structures being formed above the first metal level; wherein the first via has a first height and the second via has a second height, the first height being different from the second height; wherein the first via extends to connect the first metal level to the second metal level; wherein the second via extends to connect to the first metal level but not the second metal level; damascene intermediate metal lines between the first metal level and the second metal level; and damascene signal lines above the first via and the damascene intermediate metal lines.

Abstract: A second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. A first back end of line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, a magnetic tunnel junction (MTJ) stack aligned above the via. Forming a via dielectric layer as a second back end of line (BEOL) layer, an opening, a lower metal stud in the opening, a liner on the lower metal stud and on exposed side surfaces of the opening, an upper metal stud in remaining portions of the opening, and forming a magnetic tunnel junction (MTJ) stack aligned above.

Abstract: An antenna-structure combination method includes following steps. Provide a circuit board. At least one joint hole penetrating the circuit board is formed in the circuit board. At least one electrode layer and one feeding line are formed on a periphery of the joint hole. The feeding line is electrically connected to the electrode layer. Provide a chip antenna. The chip antenna includes a base. The base has a wiring section. A fixed connection section is arranged at one end of the wiring section. The fixed connection section is formed with a conductive layer. The fixed connection section of the chip antenna penetrates the joint hole of the circuit board, so that the conductive layer is electrically fixed to the electrode layer, so that the chip antenna is fixedly connected onto the circuit board in an upright manner.

Abstract: An antenna-structure combination method includes following steps. Provide a circuit board. At least one joint hole penetrating the circuit board is formed in the circuit board. At least one electrode layer and one feeding line are formed on a periphery of the joint hole. The feeding line is electrically connected to the electrode layer. Provide a chip antenna. The chip antenna includes a base. The base has a wiring section. A fixed connection section is arranged at one end of the wiring section. The fixed connection section is formed with a conductive layer. The fixed connection section of the chip antenna penetrates the joint hole of the circuit board, so that the conductive layer is electrically fixed to the electrode layer, so that the chip antenna is fixedly connected onto the circuit board in an upright manner.

Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.