Abstract: A computer implemented method manages function execution in a container. A dispatcher in the container running in a computer system executes a function initialization in response to a first request for a function. The dispatcher in the container running in the computer system creates group of handlers in response to receiving a group of requests for the function. The dispatcher in the container running in the computer system sends the group of requests to the group of handlers in response to receiving the group of requests. The dispatcher in the container running in the computer system executes the group of requests using the group of handlers.

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Abstract: A computer-implemented method, in accordance with one embodiment, includes generating multiple versions of software from the same source code. Each of the versions is installed onto a corresponding, unique hardware system, the hardware systems being redundant relative to one another. When the versions are run on the respective hardware systems, the resulting respective executions of the versions are different.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes receiving an input/output (I/O) transaction from an I/O device requesting data stored memory from a virtual machine. The I/O transaction includes a virtual memory address and a bus device function. The method also includes associating the I/O transaction with a key slot associated with the virtual machine and retrieving, using the key slot, an encryption key used to encrypt and decrypt the data. The method further includes retrieving the data located at a physical memory address in physical memory relating to the virtual memory address of the data being requested and decrypting, during a read operation, the data using the encryption key for I/O transmission. The method also includes transmitting the decrypted data to the I/O device.

Abstract: One or more embodiments herein relate to a process to dynamically decrypt code of a software. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise a decryption component that, in response to an indication being received that encrypted code of a code block is to be used, can temporarily decrypt the encrypted code of the code block into decrypted code for use of the decrypted code in an unencrypted state. In an embodiment, an encryption component can obtain and encrypt code of the code block at compile time of the code block to provide the encrypted code. In an embodiment, an encryption component can write a trigger marker into the encrypted code of the code block when encrypting code of the code block to provide the encrypted code.

Abstract: An apparatus, a method, and a computer program product are provided that provide confidential computing on virtual machines by securing input/output operations between a virtual machine and a device. The method includes establishing an input/output (I/O) device with an encryption key associated with a virtual machine and transmitting, by the I/O device, an I/O transaction requesting encrypted data stored in physical memory by the virtual machine. the I/O transaction includes a direct memory access (DMA) memory address and a bus device function. The method also includes retrieving, by an input/output memory management unit (IOMMU), the encrypted data mapped from the DMA memory address to a physical memory address in the physical memory and transmitting, by the IOMMU, the encrypted data to the I/O device. The method further includes decrypting, by the I/O device, the encrypted data using the encryption key associated with the virtual machine and processing the decrypted data.

Abstract: Techniques for managing and processing of configuration changes associated with a service container associated with a service mesh are presented. An application management component can determine immutable configuration data (ICD) relating to configuration change processing for the service container based on policies received from an application owner. A message processing component (MMC) of a service proxy associated with the service container can receive, via a control plane, a message associated with an untrusted entity. MMC can determine whether the message comprises a configuration change request relating to interaction between the application and the service mesh, and, if so, can determine whether to allow the service proxy to process the configuration change based on analysis of the configuration change and ICD. If ICD indicates the configuration change is not allowed, service proxy can discard the request.

Abstract: A computer implemented method for assessing endpoint security includes identifying a size of exposed PCIe space corresponding to a system of interest comprising one or more endpoints, determining an observable state of correct functionality for the system, generating random transaction layer packets corresponding to the endpoint, injecting the generated transaction layer packets, monitoring the system following the injection of the generated transaction layer packets for erroneous patterns exhibited by the system, and reporting the erroneous patterns exhibited by the system. A corresponding computer program product and computer system are also disclosed.

Abstract: Tasks of directed acyclic graphs (DAGs) may be dynamically scheduled based on a plurality of constraints and conditions, task prioritization policies, task execution estimates, and configurations of a heterogenous system. A machine learning component may be initialized to dynamically schedule the tasks of the DAGs.

Abstract: In an approach to extending the lifespan of a flash-based storage device, responsive to receiving a signal from a storage device that the storage device is low on extra blocks, one or more free logical blocks that are no longer needed are released. The storage device is notified of the one or more free logical blocks that are no longer needed. Responsive to determining that the number of valid physical blocks is greater than the number of used logical blocks, the advertised capacity of the storage device is reduced.

Abstract: Systems and methods for monitoring current anomaly are described. In an example, a device can measure first current flowing along a first liner between an instrument to an equipment. The device can measure second current flowing along a second line between the equipment to the instrument. The device can compare the measurements of the first current and the second current. The device can identify a presence of current anomaly based on the comparison of the measurements of the first and second currents. The device can, in response to the presence of the current anomaly, disconnect the instrument from the equipment.

Abstract: A flash translation layer method, system, and computer program product, include performing a virtualization of a meta-flash translation layer by: instantiating a range in a NAND chip comprising the number of free blocks using a meta-FTL to create a compatible range of blocks for a type of a feature and a flash characteristic of a translation table if a number of free blocks are available in the NAND chip and instantiating a second range in the NAND chip comprising a second number of free blocks using the meta-FTL to create a second compatible range of blocks for a second type of feature and a second flash characteristic of the translation table, and dynamically programming data on the fly based on an input requirement of a request into the range and the second range.

Abstract: Techniques for power savings in communications equipment are provided. The computer-implemented method can comprise identifying, by an electronic device operatively coupled to a processing unit, one or more connectivity requirements of one or more servers associated with a data center. The computer-implemented method can also comprise determining, by the electronic device, a defined graph that satisfies the one or more connectivity requirements. The computer-implemented method can further comprise powering down, by the electronic device, one or more elements of the data center that are not required by the defined graph; and powering up, by the device one or more nodes of the data center, which are in any state other than power up, that are required by the defined graph.

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous system-on-chip and communicatively coupled to a scheduler, where the directed acyclic graph corresponds to a control flow graph of respective tasks associated with an application executed by the heterogeneous system-on-chip. The techniques further including determining, using a learning agent implementing machine learning algorithms, a rank for a respective task in the directed acyclic graph, wherein the learning agent receives as input the directed acyclic graph, constraints associated with the directed acyclic graph, and heuristics regarding previously completed tasks. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous system-on-chip according to the rank.

Abstract: Described are techniques for scheduling tasks on a heterogeneous system on a chip (SoC). The techniques including receiving a directed acyclic graph at a meta pre-processor associated with a heterogeneous SoC and communicatively coupled to a scheduler, wherein the directed acyclic graph corresponds to a control flow graph of tasks associated with an application executed by the heterogeneous SoC. The techniques further including determining a rank for a respective task in the directed acyclic graph, wherein the rank is based on a priority of the respective task and a slack in the directed acyclic graph. The techniques further including providing the respective task to the scheduler for execution on the heterogeneous SoC according to the rank.

Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.