Patents by Inventor Hui Chang

Hui Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071656
    Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: February 29, 2024
    Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
  • Patent number: 11917193
    Abstract: According to the present invention, an image encoding apparatus comprises: a motion prediction unit which derives motion information on a current block in the form of the motion information including L0 motion information and L1 motion information; a motion compensation unit which performs a motion compensation for the current block on the basis of at least one of the L0 motion information and L1 motion information so as to generate a prediction block corresponding to the current block; and a restoration block generating unit which generates a restoration block corresponding to the current block based on the prediction block. According to the present invention, image encoding efficiency can be improved.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 27, 2024
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, University-Industry Cooperation Group of Kyung Hee University
    Inventors: Hui Yong Kim, Gwang Hoon Park, Kyung Yong Kim, Sang Min Kim, Sung Chang Lim, Jin Ho Lee, Jin Soo Choi, Jin Woong Kim
  • Patent number: 11912623
    Abstract: A fluidized solidified soil based on gold tailings includes the following raw materials in parts by mass: 75 parts to 80 parts of gold tailings, 5.2 parts to 13 parts of a dispersant solution, and 9 parts to 16 parts of a solidifying material. A preparation method includes the following steps: mixing the gold tailings with the dispersant solution, and then stirring to obtain a suspension slurry of the gold tailings; and adding the solidifying material, and stirring to obtain the fluidized solidified soil. In the present disclosure, the gold tailings are used as a main material, combined with a special dispersant solution and a special solidifying material, and a fluidized solidified soil is prepared with fluidity suitable for pumping and a certain strength after hardening. The fluidized solidified soil prevents the pollution caused by gold tailings landfilling, and can be used as a filling material for various construction projects.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: February 27, 2024
    Assignees: WUHAN INSTITUTE OF TECHNOLOGY, The College of Post and Telecommunication of WIT
    Inventors: Zunqun Xiao, Caiyun Xu, Fuqi Wang, Jian Lin, Hui Wang, Zhentao Lv, Yanbin Chang, Haitao Liu, Yinlei Shi, Keqi Luo, Minghui Deng, Puyu Li, Yuepeng Zheng
  • Patent number: 11917148
    Abstract: Disclosed herein are a video decoding method and apparatus and a video encoding method and apparatus. In video encoding and decoding, multiple partition blocks are generated by splitting a target block. A prediction mode is derived for at least a part of the multiple partition blocks, among the multiple partition blocks, and prediction is performed on the multiple partition blocks based on the derived prediction mode. When prediction is performed on the partition blocks, information related to the target block may be used, and information related to an additional partition block, which is predicted prior to the partition block, may be used.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 27, 2024
    Assignees: Electronics And Telecommunications Research Institute, Industry-University Cooperation Foundation Korea Aerospace University, Hanbat National University Industry-Academic Cooperation Foundation
    Inventors: Jin-Ho Lee, Jung-Won Kang, Hyunsuk Ko, Sung-Chang Lim, Dong-San Jun, Ha-Hyun Lee, Seung-Hyun Cho, Hui-Yong Kim, Hae-Chul Choi, Dae-Hyeok Gwon, Jae-Gon Kim, A-Ram Back
  • Publication number: 20240058241
    Abstract: Disclosed herein is a skin whitening composition that includes, based on a total volume of the skin whitening composition, 0.5 ?M to 10 ?M of resveratrol, and 2.5 ?M to 500 ?M of nicotinamide mononucleotide.
    Type: Application
    Filed: January 19, 2023
    Publication date: February 22, 2024
    Inventors: Tsong-Min CHANG, Shr-Shiuan WANG, Yi-Chang LI, Huey-Chun HUANG, Ya-Hui CHANG, Hui-Hsin YANG
  • Patent number: 11908731
    Abstract: A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tse Lai, Ya Hui Chang
  • Publication number: 20240055280
    Abstract: A method of removing a sacrificial substructure from a support structure is disclosed. The method includes receiving the support structure, where the support structure has the sacrificial substructure connected thereto, the sacrificial substructure having functioning electrical devices removed therefrom. The method also includes applying a barrier to the sacrificial substructure, puncturing the sacrificial substructure with a puncture plate to secure the sacrificial substructure to the puncture plate, and detaching the sacrificial substructure from the support structure by moving the puncture plate with respect to the support structure.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Inventors: Chen Liang Chang, Kuo Hui Chang, Ryder Su, Chi-Chun Peng
  • Patent number: 11898816
    Abstract: A muzzle flash simulator for use in an airsoft gun, comprising an internal passage, a detector, a controller, and multiple illuminating components. In response to a projectile passing through and away from the internal passage, the simulator will be triggered and flash multi-color lights on a projectile passage in front of the simulator. When each color light is illuminated on the moving projectile at a specific intensity at specified time periods, because of an afterimage phenomenon of the human eye, the surface of the moving projectile reflects the corresponding color and leaves a multi-layered light-trail accordingly.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: February 13, 2024
    Assignee: ACETK CORP LTD.
    Inventor: Yung-Hui Chang
  • Publication number: 20240047255
    Abstract: A wafer alignment assembly is provided. The wafer alignment assembly includes: a first tapered wall extending in a first horizontal direction; a first spring wall attached to an inner surface of the first tapered wall; a first set of conveyor rollers configured to rotate; a second tapered wall extending in the first horizontal direction, wherein the first tapered wall and the second tapered wall are characterized by a tapered shape that facilitates entry of a wafer assembly; a second spring wall attached to an inner surface of the first tapered wall; and a second set of conveyor rollers configured to rotate.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: Chia-Ching Lee, Tung-Hsuan Tsai, Hsin-Tai Wang, Chen Liang Chang, Kuo Hui Chang, Chi-Chun Peng
  • Publication number: 20240047209
    Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Publication number: 20240038571
    Abstract: At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Po-Yo SU, Young-Wei LIN, Yu Liang HUANG, Chia-Ching LEE, Chi-Chun PENG, Chen Liang CHANG, Kuo Hui CHANG
  • Publication number: 20240019787
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 18, 2024
    Inventors: Ru-Gun LIU, Huicheng Chang, Chia-Cheng Chen, Jyu-Horng Shieh, Liang-Yin Chen, Shu-Huei Suen, Wei-Liang Lin, Ya Hui Chang, Yi-Nien Su, Yung-Sung Yen, Chia-Fong Chang, Ya-Wen Yeh, Yu-Tien Shen
  • Patent number: 11862465
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
  • Publication number: 20230411156
    Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.
    Type: Application
    Filed: July 31, 2023
    Publication date: December 21, 2023
    Inventors: Chia-Cheng Chen, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Chun-Yen Chang, Chih-Kai Yang, Yu-Tien Shen, Ya Hui Chang
  • Publication number: 20230409133
    Abstract: A projection device including a casing, an operation module, a main board, and a conducting element is provided. The operation module includes an operation element and an operation circuit board. The operation element is disposed on the casing to execute a first operation. The operation circuit board is coupled to the operation element. The operation circuit board includes a wireless signal emitter and a first conducting portion. The operation circuit board generates a first operation signal in response to the first operation, and the wireless signal emitter emits the first operation signal. The main board includes a wireless signal receiver and a second conducting portion. The wireless signal receiver is configured to receive the first operation signal, and the main board is configured to execute a first action corresponding to the first operation signal. The conducting element is electrically connected to the first conducting portion and the second conducting portion.
    Type: Application
    Filed: June 17, 2023
    Publication date: December 21, 2023
    Applicant: Coretronic Corporation
    Inventors: Chih-Hui Chang, Jeng-An Liao
  • Publication number: 20230387008
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: providing a substrate; forming an ion implantation area in the substrate, an upper surface of the ion implantation area having a distance from an upper surface of the substrate; forming an initial word line trench in the substrate, the initial word line trench extending from the upper surface of the substrate into the ion implantation area; widening the initial word line trench to form a word line trench, a width of a bottom of the word line trench being greater than a minimum width of the word line trench.
    Type: Application
    Filed: August 15, 2022
    Publication date: November 30, 2023
    Inventors: Yongxiang LI, Min-Hui Chang
  • Publication number: 20230389266
    Abstract: Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Xiaoling WANG, Hai-Han Hung, Min-Hui Chang
  • Publication number: 20230386834
    Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Chih-Kai YANG, Yu-Tien SHEN, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Publication number: 20230377900
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 23, 2023
    Inventors: Chih-Min HSIAO, Chih-Ming LAI, Chien-Wen LAI, Ya HuI CHANG, Ru-Gun LIU
  • Publication number: 20230369047
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.
    Type: Application
    Filed: July 30, 2023
    Publication date: November 16, 2023
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen