Patents by Inventor Hui-Jung Tsai
Hui-Jung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210082858Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.Type: ApplicationFiled: November 29, 2020Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
-
Publication number: 20210082745Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: ApplicationFiled: November 16, 2020Publication date: March 18, 2021Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
-
Publication number: 20210035928Abstract: A method including the following steps is provided. A seed layer is formed. Conductive patterns are formed on the seed layer. An etching process with an etchant is performed to remove a portion of the seed layer exposed by the conductive patterns, wherein the etchant includes: 0.1 wt % to 10 wt % of phosphoric acid (H3PO4), 0.1 wt % to 10 wt % of hydrogen peroxide (H2O2), 1 ppm to 20000 ppm of a protective agent, 1 ppm to 20000 ppm of a wetting agent, and a balance amount of a solvent.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang, Tai-Min Chang
-
Patent number: 10892228Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.Type: GrantFiled: May 20, 2019Date of Patent: January 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
-
Patent number: 10886231Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.Type: GrantFiled: October 11, 2018Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai, Chen-Hua Yu
-
Patent number: 10879199Abstract: The present disclosure provides a method of fabricating an integrated fan-out package including the following steps. A semiconductor die is laterally encapsulated by an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die. A forming method of the redistribution circuit structure includes the following steps. A conductive wiring is formed over the insulating encapsulant and the semiconductor die. A dielectric material is formed on the insulating encapsulant and the semiconductor die to cover the conductive wiring. A sacrificial layer is formed on the dielectric material, wherein a first top surface of the sacrificial layer is flatter than a second top surface of the dielectric material.Type: GrantFiled: August 7, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
-
Patent number: 10879161Abstract: Conductive structures, semiconductor packages and methods of forming the same are disclosed. A semiconductor package includes at least one die and a redistribution layer. The redistribution layer is disposed over and electrically to the at least one die and includes a seed layer structure and a metal feature over the seed layer structure. In some embodiments, an edge of the seed layer structure is protruded from an edge of the metal feature and has a surface roughness Rz greater than 10 nm.Type: GrantFiled: June 5, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng, Chien-Tang Peng
-
Publication number: 20200395319Abstract: The present disclosure provides a method of manufacturing a semiconductor package. Semiconductor dies having conductive pillars are provided and are encapsulated with an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor dies, and the redistribution circuit structure is electrically connected to the semiconductor dies. A photosensitive mask pattern having a plurality of openings is formed. A plurality of conductive vias is formed within the openings of the photosensitive mask pattern. A dielectric layer is then formed, and the conductive vias are embedded in the dielectric layer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
-
Patent number: 10867874Abstract: A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder and the conductive post with a plurality of etching processes, the plurality of etching processes including a first etching process, the first etching process comprising etching the conductive post with a nitric-based etchant.Type: GrantFiled: January 21, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hui-Jung Tsai, Yun Chen Hsieh, Hung-Jui Kuo
-
Patent number: 10867827Abstract: An alignment holder for holding and testing a composite specimen includes a holder body, a supporter, and a positioning mechanism. The holder body is configured to clamp a first side of the composite specimen. The supporter is detachably connected to a lower part of the holder body for supporting a lower surface of the composite specimen. The positioning mechanism is configured to lean against a second side of the composite specimen and move relatively to the holder body for adjusting a clamping position of the composite specimen clamped by the holder body.Type: GrantFiled: April 23, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih Wang, Hung-Jui Kuo, Hui-Jung Tsai
-
Patent number: 10854570Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.Type: GrantFiled: July 4, 2018Date of Patent: December 1, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
-
Patent number: 10847429Abstract: Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.Type: GrantFiled: October 17, 2019Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Chih Wang
-
Patent number: 10840129Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: GrantFiled: December 17, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
-
Publication number: 20200343179Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin, Jyun-Siang Peng
-
Publication number: 20200303211Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.Type: ApplicationFiled: June 4, 2020Publication date: September 24, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
-
Publication number: 20200243465Abstract: A semiconductor structure includes a first substrate including a first pad thereover, a second substrate including a bump thereover and a dielectric material. The first pad includes an inner portion and an outer portion being higher than and surrounding the inner portion. The bump is bonded to the inner portion and surrounded by the outer portion. The dielectric material is disposed between the first substrate and the second substrate to encapsulate the first pad and the bump.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang
-
Patent number: 10707094Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.Type: GrantFiled: April 29, 2019Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
-
Publication number: 20200135673Abstract: The present disclosure provides a method of fabricating an integrated fan-out package including the following steps. A semiconductor die is laterally encapsulated by an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die. A forming method of the redistribution circuit structure includes the following steps. A conductive wiring is formed over the insulating encapsulant and the semiconductor die. A dielectric material is formed on the insulating encapsulant and the semiconductor die to cover the conductive wiring. A sacrificial layer is formed on the dielectric material, wherein a first top surface of the sacrificial layer is flatter than a second top surface of the dielectric material.Type: ApplicationFiled: August 7, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
-
Publication number: 20200126850Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.Type: ApplicationFiled: December 17, 2019Publication date: April 23, 2020Inventors: Hung-Jui Kuo, Yun Chen Hsieh, Hui-Jung Tsai
-
Patent number: 10629540Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.Type: GrantFiled: July 6, 2018Date of Patent: April 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko