Patents by Inventor Hui-Jung Wu
Hui-Jung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180240667Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.Type: ApplicationFiled: February 12, 2018Publication date: August 23, 2018Inventors: Jengyi Yu, Samantha Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
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Publication number: 20180211846Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.Type: ApplicationFiled: January 18, 2018Publication date: July 26, 2018Inventors: Hui-Jung Wu, Thomas Joseph Knisley, Nagraj Shankar, Meihua Shen, John Hoang, Prithu Sharma
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Patent number: 9899234Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.Type: GrantFiled: June 30, 2014Date of Patent: February 20, 2018Assignee: Lam Research CorporationInventors: Hui-Jung Wu, Thomas Joseph Knisley, Nagraj Shankar, Meihua Shen, John Hoang, Prithu Sharma
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Patent number: 9418889Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.Type: GrantFiled: June 17, 2015Date of Patent: August 16, 2016Assignee: Lam Research CorporationInventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
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Publication number: 20150380272Abstract: Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Hui-Jung Wu, Thomas Joseph Knisley, Nagraj Shankar, Meihua Shen, John Hoang, Prithu Sharma
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Publication number: 20150380302Abstract: A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.Type: ApplicationFiled: June 17, 2015Publication date: December 31, 2015Inventors: Thomas Weller Mountsier, Hui-Jung Wu, Bhadri N. Varadarajan, Nagraj Shankar, William T. Lee
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Publication number: 20140216336Abstract: Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.Type: ApplicationFiled: April 3, 2014Publication date: August 7, 2014Applicant: Novellus Systems, Inc.Inventors: Jengyi Yu, Gengwei Jiang, Pramod Subramonium, Roey Shaviv, Hui-Jung Wu, Nagraj Shankar
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Patent number: 8753978Abstract: Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.Type: GrantFiled: June 1, 2012Date of Patent: June 17, 2014Assignee: Novellus Systems, Inc.Inventors: Jengyi Yu, Gengwei Jiang, Pramod Subramonium, Roey Shaviv, Hui-Jung Wu, Nagraj Shankar
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Publication number: 20130143401Abstract: Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.Type: ApplicationFiled: June 1, 2012Publication date: June 6, 2013Inventors: Jengyi Yu, Gengwei Jiang, Pramod Subramonium, Roey Shaviv, Hui-Jung Wu, Nagraj Shankar
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Patent number: 8268722Abstract: Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH3, H2, N2, and mixtures thereof. A dielectric diffusion barrier layer is then deposited.Type: GrantFiled: January 15, 2010Date of Patent: September 18, 2012Assignee: Novellus Systems, Inc.Inventors: Jengyi Yu, Hui-Jung Wu, Girish Dixit, Bart van Schravendijk, Pramod Subramonium, Gengwei Jiang, George Andrew Antonelli, Jennifer O'loughlin
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Patent number: 8173537Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.Type: GrantFiled: March 29, 2007Date of Patent: May 8, 2012Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Hui-Jung Wu, Bart van Schravendijk, Kimberly Branshaw
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Publication number: 20120083134Abstract: Systems, methods, and apparatus for depositing a protective layer on a wafer substrate are disclosed. In one aspect, a protective layer is deposited over a surface of a wafer substrate using a process configured to produce substantially less damage in the wafer substrate than a first plasma-assisted deposition process. The protective layer is less than about 100 Angstroms thick. A barrier layer is deposited over the protective layer using the first plasma-assisted deposition process.Type: ApplicationFiled: September 15, 2011Publication date: April 5, 2012Inventors: Hui-Jung WU, Kay SONG, Victor LU, Kie Jin PARK, Wai-Fan YAU
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Patent number: 8124522Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.Type: GrantFiled: April 11, 2008Date of Patent: February 28, 2012Assignee: Novellus Systems, Inc.Inventors: Hui-Jung Wu, Kimberly Shafi, Kaushik Chattopadhyay, Keith Fox, Tom Mountsier, Girish Dixit, Bart van Schravendijk, Elizabeth Apen
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Patent number: 8021486Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: January 26, 2010Date of Patent: September 20, 2011Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu
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Patent number: 8017523Abstract: Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer, with the pure copper seed layer is deposited on the copper alloy seed layer. The copper seed bilayers have reduced line resistance increase and better electromigration performance than conventional doped copper seed layers. Precise line resistance control is achieved by tuning the bilayer thickness to meet the desired electromigration performance.Type: GrantFiled: May 16, 2008Date of Patent: September 13, 2011Assignee: Novellus Systems, Inc.Inventors: Hui-Jung Wu, Daniel R. Juliano, Wen Wu, Girish Dixit
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Publication number: 20100308463Abstract: Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu—O bonds is contacted with trimethylaluminum to form a precursor layer having Al—O bonds and Al—C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al—N, Al—H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH3, H2, N2, and mixtures thereof. A dielectric diffusion barrier layer is then deposited.Type: ApplicationFiled: January 15, 2010Publication date: December 9, 2010Inventors: Jengyi Yu, Hui-Jung Wu, Girish Dixit, Bart van Schravendijk, Pramod Subramonium, Gengwei Jiang, George Andrew Antonelli, Jennifer O'loughlin
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Patent number: 7704873Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: March 20, 2007Date of Patent: April 27, 2010Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu
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Patent number: 7576006Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.Type: GrantFiled: July 30, 2007Date of Patent: August 18, 2009Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Mandyam Sriram, Roey Shaviv, Kaushik Chattopadhyay, Hui-Jung Wu
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Publication number: 20060068540Abstract: A method to fill a valley on a substrate comprises depositing a first material onto the substrate using a chemical vapor deposition process to partially fill the valley and depositing a second material onto the substrate using a spin-on deposition process to completely fill the valley. The chemical vapor deposition process may comprise a high-density plasma chemical vapor deposition process or a low-pressure chemical vapor deposition process. The method may further comprise depositing a sacrificial layer, performing a first curing process on the first and second materials, polishing at least the sacrificial layer to remove at least a portion of the second material, and performing a second curing process on the first and second materials.Type: ApplicationFiled: September 27, 2004Publication date: March 30, 2006Inventors: Kyu Min, Hui-Jung Wu
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Publication number: 20050182151Abstract: Methods are presented herein for forming thermally stable, adhesive, low dielectric constant polyorganosilicon dielectric films for use as semiconductor insulators and as adhesion promoters as and in conjunction with low k materials. Surprisingly, the methods described herein can provide polyorganosilicon materials, coatings and films having very low dielectric constants that are generated from specified polycarbosilane starting materials employing wet coating and standard high energy generating processes, without the need for exotic production techniques or incurring disadvantages found in other low k dielectric film-forming methods. The polycarbosilane compounds, polyorganosilane compounds, adhesion promoter materials and layered materials disclosed herein can be used in any suitable semiconductor or electronic application, including semiconductor devices, electronic devices, films and coatings.Type: ApplicationFiled: January 3, 2005Publication date: August 18, 2005Inventors: Paul Apen, Hui-Jung Wu