Patents by Inventor Hui-Min Huang

Hui-Min Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200410949
    Abstract: A display device includes a substrate, a plurality of scan lines and a plurality of data lines. The data lines respectively have a first segment that overlaps one of the scan lines and a second segment that is located between adjacent two of the scan lines. A first segment of a first data line and a first segment of a second data line are separated by a distance Wa. A first segment of a third data line and a first segment of a fourth data line are separated by a distance Wc. A second segment of the first data line and a second segment of the second data line are separated by a distance W1. A second segment of the third data line and a second segment of the fourth data line are separated by a distance W3. The distances Wa, Wc, W1 and W3 have a relationship (W1/Wa)?(W3/Wc).
    Type: Application
    Filed: June 14, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Min Yeh, Hui-Min Huang, Hsieh-Li Chou, Cheng-Tso Chen, Yu-Chien Kao, Li-Wei Sung
  • Publication number: 20200395323
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Inventors: Wen-Hsiung LU, Chang-Jung HSUEH, Chin-Wei KANG, Hui-Min HUANG, Wei-Hung LIN, Cheng-Jen LIN, Ming-Da CHENG, Chien-Chun WANG
  • Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 10840111
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20200350197
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10770014
    Abstract: A display device includes a display panel having a display region and a peripheral region. The display panel includes a substrate and a scan driving circuit. The scan driving circuit disposed on the substrate includes a plurality of scan driving blocks and a plurality of first conductive lines. The first conductive lines are respectively coupled to and disposed between adjacent scan driving blocks. The scan driving blocks are disposed corresponding to the peripheral region, and the first conductive lines are disposed corresponding to the display region and the peripheral region.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 8, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Min Yeh, Hung-Hsun Chen, Hui-Min Huang, Cheng-Tso Chen, Li-Wei Sung
  • Publication number: 20200243370
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200144206
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: December 16, 2019
    Publication date: May 7, 2020
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10642118
    Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 5, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Hung-Kun Chen, Yi-Chin Lee, Hong-Kang Chang, Yu-Chien Kao, Jui-Ching Chu, Li-Wei Sung, Hui-Min Huang
  • Patent number: 10620656
    Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: April 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chih-Cheng Lin, Kai-Yin Liu, Hui-Min Huang
  • Patent number: 10622240
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10600709
    Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Chih-Wei Lin, Kuei-Wei Huang, Hui-Min Huang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10546537
    Abstract: A display device includes a display panel and display drivers disposed on the display panel. The distance between a first display driver and a second display driver of the display drivers is greater than the distance between a second display driver and a third display driver of the display drivers. The display panel includes a curved segment adjacent to an area between the first display driver and the second display driver.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: January 28, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Yi-Cheng Tsai, Cheng-Tso Chen, Hui-Min Huang, Li-Wei Sung
  • Patent number: 10510716
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10510719
    Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Meng-Tse Chen, Hui-Min Huang, Chih-Fan Huang, Ming-Da Cheng
  • Patent number: 10510697
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20190304392
    Abstract: A display device includes a display panel having a display region and a peripheral region. The display panel includes a substrate and a scan driving circuit. The scan driving circuit disposed on the substrate includes a plurality of scan driving blocks and a plurality of first conductive lines. The first conductive lines are respectively coupled to and disposed between adjacent scan driving blocks. The scan driving blocks are disposed corresponding to the peripheral region, and the first conductive lines are disposed corresponding to the display region and the peripheral region.
    Type: Application
    Filed: March 12, 2019
    Publication date: October 3, 2019
    Inventors: Chia-Min YEH, Hung-Hsun CHEN, Hui-Min HUANG, Cheng-Tso CHEN, Li-Wei SUNG
  • Publication number: 20190273068
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Application
    Filed: April 29, 2019
    Publication date: September 5, 2019
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Publication number: 20190265568
    Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 29, 2019
    Inventors: Hung-Kun CHEN, Yi-Chin LEE, Hong-Kang CHANG, Yu-Chien KAO, Jui-Ching CHU, Li-Wei SUNG, Hui-Min HUANG
  • Publication number: 20190261512
    Abstract: A display device includes: a substrate having a display area and non-display area; a first conductive layer disposed on the substrate and corresponding to the display area; a second conductive layer disposed on the substrate and corresponding to the display area, wherein the first and second conductive layers cross from top view; a first insulating layer disposed between the first and second conductive layers; a third conductive layer disposed on the substrate, corresponding to the non-display area, and including a first connection line; and a second insulating layer disposed between the second and third conductive layers. The first connection line electrically connects to the first or second conductive layer. The result of a sheet impedance of the first connection line divided by a sheet impedance of the first or second conductive layer is greater than 0 and less than or equal to 10.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 22, 2019
    Inventors: Hui-Min HUANG, Li-Wei SUNG, Cheng-Tso CHEN, Chia-Min YEH