Patents by Inventor Hui Nie
Hui Nie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150340514Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.Type: ApplicationFiled: July 30, 2015Publication date: November 26, 2015Applicant: AVOGY, INC.Inventors: Don Disney, Isik C. Kizilyalli, Hui Nie, Linda Romano, Richard J. Brown, Madhan Raj
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Patent number: 9196679Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.Type: GrantFiled: January 12, 2015Date of Patent: November 24, 2015Assignee: AVOGY, INC.Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
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Publication number: 20150325677Abstract: A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 ?m thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: AVOGY, INC.Inventors: David P. Bour, Linda Romano, Thomas R. Prunty, Izik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown
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Patent number: 9184305Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.Type: GrantFiled: August 4, 2011Date of Patent: November 10, 2015Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Patent number: 9178099Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.Type: GrantFiled: April 19, 2012Date of Patent: November 3, 2015Assignee: ALTA DEVICES, INC.Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
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Patent number: 9171900Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.Type: GrantFiled: August 7, 2014Date of Patent: October 27, 2015Assignee: AVOGY, INC.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown, Donald R. Disney
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Patent number: 9171937Abstract: An integrated device including a vertical III-nitride FET and a Schottky diode includes a drain comprising a first III-nitride material, a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, and a channel region comprising a third III-nitride material coupled to the drift region. The integrated device also includes a gate region at least partially surrounding the channel region, a source coupled to the channel region, and a Schottky contact coupled to the drift region. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride FET and the Schottky diode is along the vertical direction.Type: GrantFiled: December 17, 2014Date of Patent: October 27, 2015Assignee: AVOGY, INC.Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Patent number: 9171923Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.Type: GrantFiled: June 9, 2014Date of Patent: October 27, 2015Assignee: Avogy, Inc.Inventors: Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
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Patent number: 9171751Abstract: A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.Type: GrantFiled: April 29, 2014Date of Patent: October 27, 2015Assignee: Avogy, Inc.Inventors: Donald R. Disney, Andrew P. Edwards, Hui Nie, Richard J. Brown, Isik C. Kizilyalli, David P. Bour, Linda Romano, Thomas R. Prunty
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Patent number: 9159784Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.Type: GrantFiled: November 17, 2011Date of Patent: October 13, 2015Assignee: Avogy, Inc.Inventors: Linda Romano, Andrew P. Edwards, Richard J. Brown, David P. Bour, Hui Nie, Isik C. Kizilyalli, Thomas R. Prunty, Mahdan Raj
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Patent number: 9159799Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.Type: GrantFiled: April 19, 2013Date of Patent: October 13, 2015Assignee: Avogy, Inc.Inventors: Isik C. Kizilyalli, Dave P. Bour, Thomas R. Prunty, Hui Nie, Quentin Diduck, Ozgur Aktas
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Patent number: 9136418Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.Type: GrantFiled: April 19, 2012Date of Patent: September 15, 2015Assignee: ALTA DEVICES, INC.Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
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Patent number: 9136116Abstract: A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.Type: GrantFiled: August 4, 2011Date of Patent: September 15, 2015Assignee: Avogy, Inc.Inventors: David P. Bour, Thomas R. Prunty, Linda Romano, Andrew P. Edwards, Isik C. Kizilyalli, Hui Nie, Richard J. Brown, Mahdan Raj
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Patent number: 9136417Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.Type: GrantFiled: April 19, 2012Date of Patent: September 15, 2015Assignee: ALTA DEVICES, INC.Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
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Patent number: 9123533Abstract: A method of regrowing material includes providing a III-nitride structure including a masking layer and patterning the masking layer to form an etch mask. The method also includes removing, using an in-situ etch, a portion of the III-nitride structure to expose a regrowth region and regrowing a III-nitride material in the regrowth region.Type: GrantFiled: August 10, 2012Date of Patent: September 1, 2015Assignee: Avogy, Inc.Inventors: David P. Bour, Thomas R. Prunty, Hui Nie, Madhan M. Raj
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Publication number: 20150243758Abstract: A vertical JFET includes a GaN substrate comprising a drain of the JFET and a plurality of patterned epitaxial layers coupled to the GaN substrate. A distal epitaxial layer comprises a first part of a source channel and adjacent patterned epitaxial layers are separated by a gap having a predetermined distance. The vertical JFET also includes a plurality of regrown epitaxial layers coupled to the distal epitaxial layer and disposed in at least a portion of the gap. A proximal regrown epitaxial layer comprises a second part of the source channel. The vertical JFET further includes a source contact passing through portions of a distal regrown epitaxial layer and in electrical contact with the source channel, a gate contact in electrical contact with a distal regrown epitaxial layer, and a drain contact in electrical contact with the GaN substrate.Type: ApplicationFiled: May 13, 2015Publication date: August 27, 2015Applicant: AVOGY, INC.Inventors: Hui Nie, Andrew P. Edwards, Isik Kizilyalli, David P. Bour, Thomas R. Prunty, Quentin Diduck
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Patent number: 9117850Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.Type: GrantFiled: August 28, 2014Date of Patent: August 25, 2015Assignee: Avogy, Inc.Inventors: Don Disney, Isik C. Kizilyalli, Hui Nie, Linda Romano, Richard J. Brown, Madhan Raj
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Publication number: 20150228835Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Brendan M. KAYES, Hui NIE, Isik C. KIZILYALLI
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Patent number: 9093591Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as solar cells. In one aspect, a device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to a back side of the device and is made of a different material and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer and at least partially within the different material at a location offset from the heterojunction. An intermediate layer is located between the absorber layer and the emitter layer and provides the offset of the p-n junction from the heterojunction, and includes a graded layer and an ungraded back window layer.Type: GrantFiled: April 19, 2012Date of Patent: July 28, 2015Assignee: ALTA DEVICES, INC.Inventors: Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
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Patent number: 9093395Abstract: A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 ?m thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.Type: GrantFiled: September 2, 2011Date of Patent: July 28, 2015Assignee: Avogy, Inc.Inventors: David P. Bour, Linda Romano, Thomas R. Prunty, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown