Patents by Inventor Hun-Dae Choi
Hun-Dae Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11888489Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.Type: GrantFiled: August 15, 2022Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junsub Yoon, Hun-Dae Choi
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Publication number: 20230253971Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.Type: ApplicationFiled: August 15, 2022Publication date: August 10, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Junsub YOON, Hun-Dae CHOI
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Patent number: 11651813Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided.Type: GrantFiled: July 20, 2021Date of Patent: May 16, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hun-Dae Choi, Ga Ram Choi
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Publication number: 20220165322Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided.Type: ApplicationFiled: July 20, 2021Publication date: May 26, 2022Inventors: Hun-Dae CHOI, Ga Ram CHOI
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Patent number: 11342011Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.Type: GrantFiled: September 4, 2020Date of Patent: May 24, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Dae Choi, Hwapyong Kim
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Patent number: 10923181Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.Type: GrantFiled: January 15, 2019Date of Patent: February 16, 2021Assignee: Samsung Electronics Co., LtdInventors: Ju Ho Jeon, Hun-Dae Choi
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Patent number: 10878869Abstract: A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.Type: GrantFiled: November 16, 2018Date of Patent: December 29, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-ho Jeon, Han-gi Jung, Hun-dae Choi
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Publication number: 20200402555Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hun-Dae CHOI, Hwapyong KIM
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Patent number: 10861516Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.Type: GrantFiled: March 19, 2019Date of Patent: December 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Dae Choi, Hwapyong Kim
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Patent number: 10748585Abstract: A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.Type: GrantFiled: March 14, 2019Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventor: Hun-Dae Choi
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Patent number: 10727826Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.Type: GrantFiled: February 22, 2019Date of Patent: July 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hun-Dae Choi, Hwa-Pyong Kim
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Patent number: 10600458Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.Type: GrantFiled: August 20, 2018Date of Patent: March 24, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Ho Jeon, Han-Gi Jung, Hun-Dae Choi
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Publication number: 20200058332Abstract: A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.Type: ApplicationFiled: March 14, 2019Publication date: February 20, 2020Applicant: Samsung Electronics Co., Ltd.Inventor: Hun-Dae CHOI
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Publication number: 20200059226Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.Type: ApplicationFiled: February 22, 2019Publication date: February 20, 2020Inventors: Hun-Dae CHOI, Hwa-Pyong KIM
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Publication number: 20200027498Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.Type: ApplicationFiled: January 15, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ju Ho Jeon, Hun-Dae Choi
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Publication number: 20200027489Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.Type: ApplicationFiled: March 19, 2019Publication date: January 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hun-Dae Choi, Hwapyong Kim
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Patent number: 10530371Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.Type: GrantFiled: April 5, 2019Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Juho Jeon, Hun-Dae Choi
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Patent number: 10491223Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.Type: GrantFiled: August 14, 2018Date of Patent: November 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hangi Jung, Hun-Dae Choi, Juho Jeon
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Publication number: 20190238141Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Juho Jeon, Hun-Dae Choi
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Patent number: 10367490Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.Type: GrantFiled: July 3, 2018Date of Patent: July 30, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Wangsoo Kim, Hangi Jung, Kiduk Park, Yoo-Chang Sung, Jae-Hun Jung, Cheongryong Cho, Hun-Dae Choi