Patents by Inventor Hung-Der Lin

Hung-Der Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9509921
    Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a data generating unit (e.g. graphic generating unit) for providing a data stream (e.g. graphical stream), and a communication interface circuit. The communication interface circuit has a mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through a channel. In the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream, and compressing the video output stream. The communication interface circuit may have another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: November 29, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yang-Hung Shih, Hung-Der Lin, Tang-Hung Po, Sau-Kwo Chiu
  • Publication number: 20150334312
    Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a data generating unit (e.g. graphic generating unit) for providing a data stream (e.g. graphical stream), and a communication interface circuit. The communication interface circuit has a mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through a channel. In the mode, the communication interface circuit merges the video output stream and the data stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the data stream, and compressing the video output stream. The communication interface circuit may have another mode provided for mixing the video output stream and the data stream to transmit a mixed video output stream through the channel.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: Yang-Hung Shih, Hung-Der Lin, Tang-Hung Po, Sau-Kwo Chiu
  • Patent number: 9137458
    Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: September 15, 2015
    Assignee: MEDIATEK INC.
    Inventors: Yang-Hung Shih, Hung-Der Lin, Tang-Hung Po, Sau-Kwo Chiu
  • Publication number: 20130265489
    Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 10, 2013
    Inventors: Yang-Hung Shih, Hung-Der Lin, Tang-Hung Po, Sau-Kwo Chiu
  • Publication number: 20130127990
    Abstract: An exemplary video processing apparatus includes a first detection unit, a second detection unit, a format conversion control unit, and a format conversion processing unit. The first detection unit detects a video format of a video input. The second detection unit detects a display capability of a display device. The format conversion control unit determines whether the video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to the detected video format, determines whether the display device supports a 3D video format or a 2D video format by referring to the detected display capability, and accordingly generates a control signal. The format conversion processing unit is controlled by the control signal to generate a video output satisfying the detected display capability according to the video input when the video input does not satisfy the detected display capability.
    Type: Application
    Filed: October 9, 2010
    Publication date: May 23, 2013
    Inventors: Hung-Der Lin, Te-Chi Hsiao, Bin-Jung Tsai, Kuan-Yi Lin, Chuang-Chi Chiou, Pin-Huan Hsu, Yang-Tse Li, Chi-Cheng Ju
  • Patent number: 7831847
    Abstract: Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: November 9, 2010
    Assignee: Mediatek Inc.
    Inventors: Wei-Jen Chen, Chien-Chung Chen, Hung-Der Lin, Siou-Shen Lin, Ching-hsiang Liao
  • Publication number: 20100128802
    Abstract: A video processing circuit includes a video generating unit for generating a video output stream, a graphic generating unit for providing a graphical stream, and a communication interface circuit coupled to the video generating unit and the graphic generating unit. The communication interface circuit has a first mode provided for mixing the video output stream and the graphical stream to transmit a mixed video output stream through a channel and a second mode provided for merging the video output stream and the graphical stream to transmit a first merged signal through the channel. In the second mode, the communication interface circuit merges the video output stream and the graphical stream by increasing a working frequency of the communication interface circuit to increase bandwidths of the channel, using positions for transmitting a portion of video control signals in the video output stream to transmit the graphical stream, and compressing the video output stream.
    Type: Application
    Filed: November 24, 2008
    Publication date: May 27, 2010
    Inventors: Yang-Hung Shih, Hung-Der Lin, Tang-Hung Po, Sau-Kwo Chiu
  • Publication number: 20080282100
    Abstract: Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Applicant: MEDIATEK INC.
    Inventors: Wei-Jen Chen, Chien-Chung Chen, Hung-Der Lin, Siou-Shen Lin, Ching-hsiang Liao