BACKGROUND OF THE INVENTION 1. Field of the Invention
The disclosed embodiments of the present invention relate to displaying video contents on a display device, and more particularly, to a video processing apparatus for generating a video output satisfying the display capability of a display device according to a video input and related method thereof.
2. Description of the Related Art
Three-dimensional (3D) video presentation technology is developed to improve the viewing entertainment of the end-users. For example, 3D glasses and 3D display devices are devised to realize the playback of the 3D video content. The 3D video content may be recorded using a full resolution scheme which transmits left-eye pictures and right-eye pictures by different bitstreams or may be recorded using a half resolution scheme which transmits a left-eye picture and a right-eye picture in each frame of a single bitstream. For example, the 3D video content may be recorded using a frame/field sequential format, a side-by-side format, a line-by-line format, a top-and-bottom format, or a checker sampling format when either of the full resolution scheme and the half resolution scheme is employed.
In a case where a 3D display device is available but a conventional video playback device fails to recognize the display capability of the 3D display device, the 3D display device may be treated as a traditional two-dimensional (2D) display device and then driven by the video playback device to show a 2D video content according to a 3D video input. As a result, there is no 3D effect perceived by the user. In another case where the 3D display device is available but no 2D-to-3D conversion is supported by the conventional video playback device, the 3D display device only shows the 2D video content without any 3D effect.
Therefore, there is a need for correctly recognizing the display capability of the display device and/or the video format of the video input to properly display the video content transmitted by the video input on the display device.
BRIEF SUMMARY OF THE INVENTION In accordance with exemplary embodiments of the present invention, a video processing apparatus for generating a video output satisfying the display capability of a display device according to a video input and related method thereof are proposed to solve the above-mentioned problem.
According to a first aspect of the present invention, an exemplary video processing apparatus is disclosed. The exemplary video processing apparatus includes a first detection unit, a second detection unit, and a format conversion control unit. The first detection unit is for detecting a video format of a video input. The second detection unit is for detecting a display capability of a display device. The format conversion control unit is coupled to the first detection unit and the second detection unit, and utilized for determining whether the video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to the detected video format, determining whether the display device supports a 3D video format or a 2D video format by referring to the detected display capability of the display device, and accordingly generating a control signal. The format conversion processing unit is coupled to the format conversion control unit, and controlled by the control signal to generate a video output which satisfies the detected display capability of the display device according to the video input when the video input does not satisfy the detected display capability.
According to a second aspect of the present invention, an exemplary video processing method is disclosed. The exemplary video processing method includes the following steps: detecting a video format of a video input; detecting a display capability of a display device; determining whether the video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to the detected video format; determining whether the display device supports a 3D video format or a 2D video format by referring to the detected display capability; and generating a video output which satisfies the detected display capability of the display device according to the video input when the video input does not satisfy the detected display capability.
According to a third aspect of the present invention, an exemplary video processing apparatus is disclosed. The exemplary video processing apparatus includes a detection unit, a format conversion control unit, and a format conversion processing unit. The detection unit is for detecting a video format of a video input. The format conversion control unit is coupled to the detection unit, and used for determining whether the video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to the detected video format, determining whether a display device supports a 3D video format or a 2D video format by referring to a predetermined display capability of the display device, and accordingly generating a control signal. The format conversion processing unit is coupled to the format conversion control unit, and controlled by the control signal to generate a video output which satisfies the predetermined display capability of the display device according to the video input when the video input does not satisfy the predetermined display capability.
According to a fourth aspect of the present invention, an exemplary video processing method is disclosed. The exemplary video processing method includes the following steps: detecting a video format of a video input; determining whether the video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to the detected video format; determining whether a display device supports a 3D video format or a 2D video format by referring to a predetermined display capability of the display device; and generating a video output which satisfies the predetermined display capability of the display device according to the video input when the video input does not satisfy the predetermined display capability.
According to a fifth aspect of the present invention, an exemplary video processing apparatus is disclosed. The exemplary video processing apparatus includes a detection unit, a format conversion control unit, and a format conversion processing unit. The detection unit is for detecting a display capability of a display device. The format conversion control unit is coupled to the detection unit, and used for determining whether a video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to a predetermined video format of the video input, determining whether the display device supports a 3D video format or a 2D video format by referring to the detected display capability, and accordingly generating a control signal. The format conversion processing unit is coupled to the format conversion control unit, and controlled by the control signal to generate a video output which satisfies the detected display capability of the display device according to the video input when the video input does not satisfy the detected display capability.
According to a sixth aspect of the present invention, an exemplary video processing method is disclosed. The exemplary video processing method includes the following steps: detecting a display capability of a display device; determining whether a video input has a three-dimensional (3D) video format or a two-dimensional (2D) video format by referring to a predetermined video format of the video input; determining whether the display device supports a 3D video format or a 2D video format by referring to the detected display capability; and generating a video output which satisfies the detected display capability of the display device according to the video input when the video input does not satisfy the detected display capability.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram illustrating a video processing apparatus according to a first exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating a first playback scenario of a video input.
FIG. 3 is a diagram illustrating a second playback scenario of the video input.
FIG. 4 is a diagram illustrating a third playback scenario of the video input.
FIG. 5 is a diagram illustrating a first exemplary 3D-to-2D conversion for processing the 3D video to generate the 2D video.
FIG. 6 is a diagram illustrating a second exemplary 3D-to-2D conversion for processing the 3D video to generate the 2D video.
FIG. 7 is a diagram illustrating a third exemplary 3D-to-2D conversion for processing the 3D video to generate the 2D video.
FIG. 8 is a diagram illustrating a fourth exemplary 3D-to-2D conversion for processing the 3D video to generate the 2D video.
FIG. 9 is a diagram illustrating a fifth exemplary 3D-to-2D conversion for processing the 3D video to generate the 2D video.
FIG. 10 is a diagram illustrating a fourth playback scenario of the video input.
FIG. 11 is a diagram illustrating a fifth playback scenario of the video input.
FIG. 12 is a diagram illustrating a storage arrangement for the video input with the frame/field sequential format.
FIG. 13 is a diagram illustrating a storage arrangement for the video input with the top-and-bottom format.
FIG. 14 is a diagram illustrating a storage arrangement for the video input with the side-by-side format.
FIG. 15 is a diagram illustrating a storage arrangement for the video input with the line-by-line format.
FIG. 16 is a diagram illustrating a first exemplary implementation of a format conversion processing unit shown in FIG. 1.
FIG. 17 is a diagram illustrating a second exemplary implementation of the format conversion processing unit shown in FIG. 1.
FIG. 18 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the frame/field sequential format.
FIG. 19 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the frame/field sequential format.
FIG. 20 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the frame/field sequential format.
FIG. 21 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the frame/field sequential format.
FIG. 22 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the top-and-bottom format.
FIG. 23 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the top-and-bottom format.
FIG. 24 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the top-and-bottom format.
FIG. 25 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the top-and-bottom format.
FIG. 26 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the side-by-side format.
FIG. 27 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the side-by-side format.
FIG. 28 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the side-by-side format.
FIG. 29 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the side-by-side format.
FIG. 30 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the line-by-line format.
FIG. 31 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the line-by-line format.
FIG. 32 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the line-by-line format.
FIG. 33 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the line-by-line format.
FIG. 34 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format.
FIG. 35 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format.
FIG. 36 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format.
FIG. 37 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format.
FIG. 38 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the checker sampling format.
FIG. 39 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the checker sampling format.
FIG. 40 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the checker sampling format.
FIG. 41 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the checker sampling format.
FIG. 42 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the checker sampling format.
FIG. 43 is a diagram illustrating a video processing apparatus according to a second exemplary embodiment of the present invention.
FIG. 44 is a diagram illustrating a video processing apparatus according to a third exemplary embodiment of the present invention.
FIG. 45 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format.
FIG. 46 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format.
FIG. 47 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format.
FIG. 48 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format.
FIG. 49 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format.
FIG. 50 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format.
FIG. 51 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format.
FIG. 52 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format.
DETAILED DESCRIPTION OF THE INVENTION Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
The conception of the present invention is to detect a video format of a video input and/or a display capability of a display device, and then generate a video output satisfying the display capability of the display device. In one exemplary embodiment, the video output is generated according to a control signal which is generated by referring to a detected video format of a video input and a detected display capability of a display device. In another exemplary embodiment, the video output is generated according to a control signal which is generated by referring to a predetermined video format of a video input and a detected display capability of a display device. In yet another exemplary embodiment, the video output is generated according to a control signal which is generated by referring to a detected video format of a video input and a predetermined display capability of a display device. In this way, an optimized display quality of the video playback, either 2D video playback or 3D video playback, can be achieved. By way of example, but not limitation, the source video format of the video input may be one of the frame/field sequential format, the side-by-side format, the line-by-line format, the top-and-bottom format, and the checker sampling format due to the full resolution scheme or the half resolution scheme, and the display video format supported by the display device may be one of the frame/field sequential format, the side-by-side format, the line-by-line format, the top-and-bottom format, and the checker sampling format due to the full resolution scheme or the half resolution scheme.
FIG. 1 is a diagram illustrating a video processing apparatus according to a first exemplary embodiment of the present invention. The exemplary video processing apparatus 100 includes, but is not limited to, a first detecting unit 102 with video source format detection functionality, a second detecting unit 104 with display capability detection functionality, a format conversion control unit 106, and a format conversion processing unit 108. The first detection unit 102 is for detecting a video format VF of a video input S_IN′, wherein the detected video format VF is to indicate whether the video input S_IN′ has a 3D video format or a 2D video format. By way of example, but not limitation, the video input S_IN′ is generated from a video decoder 120 which decodes a video bitstream (i.e., an encoded video input) S_IN provided by a video source 110 such as an optical disc. In other words, the video bitstream S_IN provided by the video source 110 has encoded pictures, and the video input S_IN′ generated from the video decoder 120 contains reconstructed/decoded pictures to be displayed. For example, the first detection unit 102 may recognize the video format VF of the video input S_IN′ by simply referring to header information embedded in the source video data. However, this is for illustrative purposes only. The first detection unit 102 may employ a different detecting scheme as long as the video format VF of the video input S_IN′ can be correctly recognized.
The second detection unit 104 is for detecting a display capability DC of a display device 130, wherein the detected display capability is to indicate whether the display device 130 supports a 3D video format or a 2D video format. By way of example, but not limitation, the second detection unit 104 determines the display capability DC of the display device 130 according to display capability information generated from the display device 130. In one exemplary embodiment of the present invention, the video processing apparatus 100 and the video decoder 120 may be disposed in a video playback device (e.g., an optical disc player or a set-top box) external to the display device 130. Therefore, the video processing apparatus 100 has a display port 109 coupled to the display device 130 through a connection cable such as a high-definition multimedia interface (HDMI) cable. That is, in this exemplary embodiment, the display port 109 may be an HDMI port capable of outputting data to the display device 130 and receiving data from the display device 130. The display capability information indicating the display capability DC of the display device 130 may be transmitted via the HDMI cable and then received by the video processing apparatus 100 via the display port 109. For example, the display capability information is included in the enhanced extended display identification data (E-EDID) received from the display device 130 via the HDMI cable. However, this is for illustrative purposes only. The second detection unit 104 may employ a different detecting scheme as long as the display capability DC of the display device 130 can be correctly recognized.
The format conversion control unit 106 is coupled to the first detection unit 102 and the second detection unit 104, and is implemented for determining whether the video input S_IN′ has a 3D video format or a 2D video format by referring to the detected video format VF, determining whether the display device 130 supports a 3D video format or a 2D video format by referring to the detected display capability DC, and accordingly generating a control signal S_C. The format conversion processing unit 108 is coupled to the format conversion control unit 106, and is controlled by the control signal S_C to generate a video output S_OUT satisfying the detected display capability DC according to the video input S_IN′ when the video input S_IN′ does not satisfy the detected display capability DC. To put it simply, when the video format of the video input S_IN′ fails to meet the playback requirement of the display device 130, the format conversion processing unit 108 is enabled to apply an adequate video format conversion upon the video input S_IN′. The operation of the format conversion processing unit 108 is detailed as follows.
Please refer to FIG. 2, which is a diagram illustrating a first playback scenario of the video input S_IN′. When the format conversion control unit 106 determines that the video input S_IN′ is a 2D video and the display device 130 is a 2D display device, the control signal S_C blocks the format conversion processing unit 108 from performing any video format conversion upon the video input S_IN′. Therefore, the video input S_IN′ is bypassed and directly serves as the video output S_OUT transmitted to the display device 130 which is a 2D display device. As a result, the output of the display device 130 simply presents the normal 2D effect to the viewer.
Please refer to FIG. 3, which is a diagram illustrating a second playback scenario of the video input S_IN′. When the format conversion control unit 106 determines that the video input S_IN′ is a 2D video and the display device 130 is a 3D display device, the control signal S_C controls the format conversion processing unit 108 to enable a 2D-to-3D conversion for processing the 2D video to generate a 3D video as the video output S_OUT transmitted to the display device 130 which is a 3D display device. As a result, the output of the display device 130 allows the viewer to have 3D viewing experience though the original video input S_IN′ is a 2D video which does not satisfy the display capability of the display device 130.
Please refer to FIG. 4, which is a diagram illustrating a third playback scenario of the video input S_IN′. When the format conversion control unit 106 determines that the video input S_IN′ is a 3D video and the display device 130 is a 2D display device, the control signal S_C controls the format conversion processing unit 108 to enable a 3D-to-2D conversion for processing the 3D video to generate a 2D video as the video output S_OUT transmitted to the display device 130 which is a 2D display device. As a result, the output of the display device 130 allows the viewer to have a natural 2D viewing experience though the original video input S_IN′ is a 3D video which does not satisfy the display capability of the display device 130.
FIG. 5-FIG. 9 are diagrams illustrating exemplary 3D-to-2D conversions for processing the 3D video to generate the 2D video, respectively. The areas marked by slash lines represent pixel data of a right-eye picture, and areas that are crossed out represent pixel data of the discarded right-eye picture. As shown in FIG. 5, the video input S_IN′ has a side-by-side format. Therefore, a cropping operation is first performed upon an input frame to thereby extract one view (e.g., a left-eye picture) and discard the other view (e.g., the right-eye picture), and then a horizontal scaling operation is performed upon the extracted view to generate a complete output frame for 2D display.
As shown in FIG. 6, the video input S_IN′ has a top-and-bottom format. Therefore, a cropping operation is first performed upon an input frame to thereby extract one view (e.g., a left-eye picture) and discard the other view (e.g., the right-eye picture) in the same input frame, and then a vertical scaling operation is performed upon the extracted view to generate a complete output frame for 2D display.
As shown in FIG. 7, the video input S_IN′ has a line-by-line format. Therefore, a cropping operation is first performed upon an input frame to thereby extract one view (e.g., a left-eye picture) and discard the other view (e.g., the right-eye picture), and then a vertical scaling operation is performed upon the extracted view to generate a complete output frame for 2D display.
As shown in FIG. 8, the video input S_IN′ has a checker sampling format. Therefore, a cropping operation is first performed upon in an input frame to thereby extract one view (e.g., a left-eye picture) and discard the other view (e.g., the right-eye picture), and then a checker 2D scaling operation is performed upon the extracted view to generate a complete output frame for 2D display.
As shown in FIG. 9, the video input S_IN′ has a frame/field sequential format. Therefore, a de-multiplexing (DeMux) operation is performed upon the video input S_IN′ to thereby select pictures of one view (e.g., left-eye pictures) and discard pictures of the other view (e.g., the right-eye pictures), where the selected pictures corresponding to the same view are transmitted to the display device 130 for 2D display.
Please refer to FIG. 10, which is a diagram illustrating a fourth playback scenario of the video input S_IN′. When the format conversion control unit 106 determines that the video input S_IN′ is a 3D video and the display device 130 is a 3D display device, the control signal S_C blocks the format conversion processing unit 108 from performing any video format conversion upon the video input S_IN′. Therefore, the video input S_IN′ is bypassed and directly serves as the video output S_OUT transmitted to the display device 130 which is a 3D display device. As a result, the output of the display device 130 simply presents the normal 3D effect to the viewer.
The video input S_IN′ which is a 3D video may have a video format being one of a plurality of 3D video formats including the frame/field sequential format, the side-by-side format, the line-by-line format, the top-and-bottom format, and the checker sampling format. In addition, the display device 130 which is a 3D display device may be configured to support a video format being one of the above-mentioned 3D video formats. If the 3D video format of the video input S_IN′ is identical to the 3D video format supported by the display device 130, no format conversion from one 3D video format to another 3D video format is required, as shown in FIG. 6. However, if the 3D video format of the video input S_IN′ is not identical to the 3D video format supported by the display device 130, a format conversion from one 3D video format to another 3D video format is still necessitated for normal video content playback.
Please refer to FIG. 11, which is a diagram illustrating a fifth playback scenario of the video input S_IN′. When the format conversion control unit 106 determines that the video input S_IN′ is a 3D video with a first video format (e.g., a side-by-side format as shown in FIG. 11) and the display device 130 is a 3D display device supporting a second video format (e.g., a frame/field sequential format) different from the first video format, the control signal S_C controls the format conversion processing unit 108 to apply a 3D-to-3D conversion for processing the video input S_IN′ with the first video format to thereby generate a 3D video with the second video format, wherein the generated 3D video serves as the video output S_OUT transmitted to the display device 130 which is a 3D display device. As a result, the output of the display device 130 allows the viewer to have the 3D viewing experience though the original video input S_IN′ has a video format not complying with the display capability of the display device 130.
Regarding these playback scenarios shown in FIG. 10 and FIG. 11, the format conversion processing unit 108 has to receive data of the video input S_IN′ which is a 3D video and generate data of the video output S_OUT to the display device 130 which is a 3D display device. The video input S_IN′ may have a video format being one of the aforementioned 3D video formats, and the display device 130 may be configured to support a video format being one of the aforementioned 3D video formats. When the video input S_IN′ complies with one of the frame/field sequential format and the top-and-bottom format, data of the left-eye picture L1 and data of the right-eye picture R1 of the video input S_IN′ are respectively stored in a first buffer BUF_1 and a second buffer BUF_2 according to a scan line mode or a block mode. The storage arrangement for the video input S_IN′ with the frame/field sequential format is identical to that of the video input S_IN′ with the top-and-bottom format. For example, regarding each of the storage arrangement for the video input S_IN′ with the frame/field sequential format and the storage arrangement for the video input S_IN′ with the top-and-bottom format, data of the right-eye picture R1 is stored into the second buffer BUF_2 only after data of the left-eye picture L1 is stored into the first buffer BUF_1, as shown in FIG. 12 and FIG. 13. The data storage order is indicated by the arrow symbols in FIG. 12 and FIG. 13. It should be noted that the left-eye picture L1 and the right-eye picture R1 are continuously stored into the first buffer BUF_1 and the second buffer BUF_2 when the video input S_IN′ has the top-and-bottom format.
In addition, when the video input S_IN′ complies with one of the side-by-side format, the line-by-line format, and the checker sampling format, data of the left-eye picture L1 and data of the right-eye picture R1 of the video input S_IN′ are both stored in the same buffer BUF. It should be noted that the storage arrangement for the video input S_IN′ with the side-by-side format is identical to that of the video input S_IN′ with the line-by-line format. For example, regarding each of the storage arrangement for the video input S_IN′ with the side-by-side format and the storage arrangement for the video input S_IN′ with the line-by-line format, partial data of the left-eye picture L1 and partial data of the right-eye picture R1 are alternately stored into the buffer BUF until all of the left-eye picture L and right-eye picture R are stored in the buffer BUF, as shown in FIG. 14 and FIG. 15. Similarly, the data storage order is indicated by the arrow symbols in FIG. 14 and FIG. 15.
No matter how the video input S_IN′ is stored in the buffer(s), the format conversion processing unit 108 is required to properly read the buffered video input S_IN′ for generating the video output S_OUT with a 3D video format supported by the display device 130. Please refer to FIG. 16, which is a diagram illustrating a first exemplary implementation of the format conversion processing unit shown in FIG. 1. The format conversion processing unit 1600 includes a first display module 1602 and a second display module 1604 acting as video output circuits. The first display module 1602 and the second display module 1604 are configured to simultaneously access buffer(s). That is, each of the first display module 1602 and the second display module 1604 can access one buffer in one data scanning clock period. Please refer to FIG. 17, which is a diagram illustrating a second exemplary implementation of the format conversion processing unit shown in FIG. 1. The format conversion processing unit 1700 includes a display module 1702 acting as a video output circuit. In one embodiment, the display module 1702 may access buffer(s) in an alternate manner. That is, the display module 1702 can access a buffer in one data scanning clock period, and access the same buffer or another buffer in another data scanning clock period. In another embodiment, the display module 1702 may be devised to randomly access data stored in buffer(s). That is, in each data scanning clock period, the display module 1702 can access any desired data stored in the buffer(s). The operations of the format conversion processing units 1600 and 1700 are summarized as follows.
Consider a first case where the video input S_IN′ complies with one of the frame/field sequential format and the top-and-bottom format, and has a first input picture and a second input picture corresponding to different views and respectively stored in a first buffer and a second buffer (e.g., left-eye picture L and right-eye picture R respectively stored in buffers BUF_1 and BUF_2 as shown in FIG. 12/FIG. 13); and the video output S_OUT complies with one of the frame/field sequential format and the top-and-bottom format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 can access one buffer in one data scanning clock period only. Therefore, the display module 1702 alternately reads data from the first input picture stored in the first buffer and reads data from the second input picture stored in the second buffer, and accordingly obtains a first video data and a second video data; outputs the first output picture according to the first video data; and outputs the second output picture according to the second video data.
Consider a second case where the video input S_IN′ complies with one of the frame/field sequential format and the top-and-bottom format, and has a first input picture and a second input picture corresponding to different views and respectively stored in a first buffer and a second buffer (e.g., left-eye picture L and right-eye picture R respectively stored in buffers BUF_1 and BUF_2 as shown in FIG. 12/FIG. 13); and the video output complies with one of the frame/field sequential format, the top-and-bottom format, the side-by-side format, the line-by-line format, and the checker sampling format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, the first display module 1602 reads data from the first buffer in which the first input picture is stored and accordingly obtains a first video data, and outputs the first output picture according to the first video data. In addition, the second display module 1604 reads data from the second buffer in which the second input picture is stored and accordingly obtains a second video data, and outputs the second output picture according to the second video data, wherein the first display module 1602 reads the first buffer and the second display module 1604 reads the second buffer, simultaneously.
Consider a third case where the video input S_IN′ complies with one of the frame/field sequential format and the top-and-bottom format, and has a first input picture and a second input picture corresponding to different views and respectively stored in a first buffer and a second buffer (e.g., left-eye picture L and right-eye picture R respectively stored in buffers BUF_1 and BUF_2 as shown in FIG. 12/FIG. 13); and the video output complies with one of the frame/field sequential format, the top-and-bottom format, the side-by-side format, the line-by-line format, and the checker sampling format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 can randomly access the different buffers in each data scanning clock period. Therefore, the display module 1702 performs a random access upon the first buffer and the second buffer for reading data from the first buffer in which the first input picture is stored and accordingly obtaining a first video data, reading data from the second buffer in which the second input picture is stored and accordingly obtaining a second video data, outputting the first output picture according to the first video data, and outputting the second output picture according to the second video data.
Consider a fourth case where the video input S_IN′ complies with one of the side-by-side and the line-by-line format, and has a first input picture and a second input picture corresponding to different views and both stored in a buffer (e.g., left-eye picture L and right-eye picture R respectively stored in the same buffer BUF as shown in FIG. 14/FIG. 15); and the video output S_OUT complies with one of the frame/field sequential format and the top-and-bottom format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 can access one buffer in one data scanning clock period only. Therefore, the display module 1702 alternately reads data from the first input picture stored in the buffer and reads data from the second input picture stored in the same buffer, and accordingly obtains a first video data and a second video data; outputs the first output picture according to the first video data; and outputs the second output picture according to the second video data.
Consider a fifth case where the video input S_IN′ complies with one of the side-by-side format and the line-by-line format, and has a first input picture and a second input picture corresponding to different views and both stored in a buffer (e.g., left-eye picture L and right-eye picture R respectively stored in the same buffer BUF as shown in FIG. 14/FIG. 15); and the video output complies with one of the frame/field sequential format, the top-and-bottom format, the side-by-side format, the line-by-line format, and the checker sampling format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access the buffer in one data scanning clock period. Therefore, the first display module 1602 reads data from the first input picture stored in the buffer and accordingly obtains a first video data, and outputs the first output picture according to the first video data. In addition, the second display module 1604 reads data from the second input picture stored in the same buffer and accordingly obtains a second video data, and outputs the second output picture according to the second video data, wherein the first display module 1602 reads data from the first input picture stored in the buffer and the second display module 1604 reads data from the second input picture stored in the buffer, simultaneously.
Consider a sixth case where the video input S_IN′ complies with one of the side-by-side format, the line-by-line format, and the checker sampling format, and has a first input picture and a second input picture corresponding to different views and both stored in a buffer (e.g., left-eye picture L and right-eye picture R respectively stored in the same buffer BUF as shown in FIG. 14/FIG. 15); and the video output S_OUT complies with one of the frame/field sequential format, the top-and-bottom format, the side-by-side format, the line-by-line format, and the checker sampling format, and has a first output picture and a second output picture corresponding to different views. The format conversion processing unit 108 shown in FIG. 1 may be realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 can randomly access the buffer in each data scanning clock period. Therefore, the display module 1702 performs a random access upon the buffer for reading data from the first input picture stored in the buffer and reading data from the second input picture stored in the buffer, and accordingly obtaining a first video data and a second video data; outputting the first output picture according to the first video data; and outputting the second output picture according to the second video data.
For better understanding of the technical features of the present invention, several exemplary data scanning operations for generating the desired video output S_OUT are illustrated using accompanying figures.
FIG. 18 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the frame/field sequential format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to access one buffer in one data scanning clock period only. Therefore, the display module 1702 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in one buffer during a first data scanning clock period, read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in another buffer during a second data scanning clock period, and accordingly obtain a first video data and a second video data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, each of the first data scanning clock period and second data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync, and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data simultaneously read from different buffers should be properly mixed such that the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
In a third exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access the buffers in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtaining a first video data; in addition, during the same data scanning clock period, the display module 1702 also performs a random access for reading data from another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtaining a second video data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 19 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the frame/field sequential format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to access one buffer in one data scanning clock period only. Therefore, the display module 1702 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in one buffer during a first data scanning clock period, read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in another buffer during a second data scanning clock period, and accordingly obtain a first video data and a second video data. By way of example, but not limitation, half of the pixel data of the left-eye picture in the video input S_IN′ is extracted as the first video data, and half of the pixel data of the right-eye picture in the video input S_IN′ is extracted as the second video data. However, in an alternative design, scaling may be applied to the data read from the buffers if necessary. In this embodiment, each of the first data scanning clock period and the second data scanning clock period may be equal to half of a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. The display module 1702 therefore generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data simultaneously read from different buffers should be properly mixed such that the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a third exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access the buffers in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtaining a first video data; in addition, during the same data scanning clock period, the display module 1702 also performs a random access for reading data from another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtaining a second video data. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 20 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the frame/field sequential format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored, and the second display module 1604 is enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored. As shown in FIG. 20, the partial scan line data of the first input picture and the partial scan line data of the second input picture are mixed to form one scan line which is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. In this way, the first display module 1602 can obtain a first video data and the second display module 1604 can obtain a second video data due to the repeated read operation for retrieving partial scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access the buffers in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and reading data from another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored. Similarly, the partial scan line data of the first input picture and the partial scan line data of the second input picture are mixed to form one scan line which is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. In this way, the display module 1702 obtains a first video data and a second video data due to the repeated read operation for retrieving partial scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 21 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the frame/field sequential format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored, and the second display module 1604 is enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored. In one implementation, the scan line data of an odd scan line read from the first input picture is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display, and the scan line data of an even scan line read from the second input picture is transmitted during the next time period between two successive pulses of the horizontal synchronization signal H-sync. Because of the alternate transmission of the scan line data read from the first input picture and the scan line data read from the second input picture under the control of the properly generated horizontal synchronization signal H-sync, the video output S_OUT with the desired line-by-line format is generated. Specifically, the first display module 1602 obtains a first video data and the second display module 1604 obtains a second video data due to the repeated read operation for retrieving the scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access the buffers in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and reading data from another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored. Similarly, the scan line data of an odd scan line read from the first input picture and the scan line data of an even scan line read from the second input picture are respectively transmitted during successive time periods each between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. In this way, the display module 1702 obtains a first video data and a second video data due to the repeated read operation for retrieving the scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 45 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format. In this exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is also enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. It should be noted that scaling may be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. As shown in FIG. 45, the first display module 1602 obtains the first video data with a plurality of black areas distributed therein, wherein each black area (i.e., a crossed-out area marked by “X”) includes pixels each having no effect on the mixed picture. Similarly, the second display module 1604 obtains the second video data with a plurality of black areas distributed therein, wherein each black area (i.e., a crossed-out area marked by “X”) includes pixels each having no effect on the mixed picture. The first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data should be properly mixed to thereby generate the video output S_OUT with the desired checker sampling format as shown in FIG. 45. Please note that the black areas have no dominant effect on the mixed result (i.e., the video output S_OUT) in this embodiment, and may have any pixel values.
FIG. 46 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format. In this exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from one buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is also enabled to read data stored in another buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. It should be noted that scaling may be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. Next, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data should be properly multiplexed to thereby generate the video output S_OUT with the desired checker sampling format as shown in FIG. 46. For example, the first display module 1602 and the second display module 1604 obtain the first video data and the second video data according to a slower data rate; however, the first display module 1602 and the second display module 1604 output the first video data and the second video data according to a faster data rate used for multiplexing the output of the first video data and the second video data. For example, in one clock cycle of a reference clock, only the first display module 1602 is allowed to output data; however, in the next clock cycle of the reference clock, only the second display module 1604 is allowed to output data.
FIG. 22 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the top-and-bottom format. FIG. 23 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the top-and-bottom format. FIG. 24 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the top-and-bottom format. FIG. 25 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the top-and-bottom format. FIG. 47 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format. FIG. 48 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format. As mentioned above, the storage arrangement for the video input S_IN′ with the frame/field sequential format is identical to that of the video input S_IN′ with the top-and-bottom format. Therefore, a person skilled in the art can readily understand details of the exemplary data scanning operations shown in FIG. 22-FIG. 25 and FIG. 47-FIG. 48 after reading above paragraphs directed to exemplary data scanning operations shown in FIG. 18-FIG. 21 and FIG. 45-FIG. 46. Further description is therefore omitted here for brevity.
FIG. 26 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the side-by-side format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to access one buffer in one data scanning clock period only. Therefore, during a first data scanning clock period, the display module 1702 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer; in addition, during a second data scanning clock period, the display module 1702 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Please note that scan line data of a scan line read from the first input picture should be properly scaled if necessary; additionally, the scan line data of a scan line read from the second input picture should be properly scaled if necessary. In this embodiment, each of the first data scanning clock period and the second data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync, and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access one buffer in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer, and the second display module 1604 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Similarly, the scan line data of a scan line read from the first input picture should be properly scaled if necessary, and the scan line data of a scan line read from the second input picture should be properly scaled if necessary. Accordingly, the first display module 1602 obtains a first video data, and the second display module 1604 obtains a second video data. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data simultaneously read from the same buffer are properly mixed such that the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
In a third exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access one buffer in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer and reading data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Similarly, scan line data of a scan line read from the first input picture should be scaled is necessary, and the scan line data of a scan line read from the second input picture should be scaled if necessary. Accordingly, the display module 1702 obtains a first video data and a second video data. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture is transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync and the second output picture is transmitted during the next time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 27 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the side-by-side format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to access one buffer in one data scanning clock period only. Therefore, during a first data scanning clock period, the display module 1702 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer; in addition, during a second data scanning clock period, the display module 1702 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Accordingly, the display module 1702 obtains a first video data and a second video data. By way of example, but not limitation, half of the pixel data of the first input picture is read and then scaled to become the first video data, and half of the pixel data of the second input picture is read and then scaled to become the second video data. It should be noted that scaling should be applied to the data read from the buffer if necessary. In this embodiment, each of the first data scanning clock period and the second data scanning clock period may be equal to a half of a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, the first display module 1602 and the second display module 1604 can simultaneously access one buffer in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer, and the second display module 1604 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Accordingly, the first display module 1602 obtains a first video data, and the second display module 1604 obtains a second video data. Similarly, scaling should be applied to the data read from the buffer if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync which is referenced for displaying. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data simultaneously read from the same buffer are properly mixed such that the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a third exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access one buffer in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer and reading data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Accordingly, the display module 1702 obtains a first video data and a second video data. Similarly, scaling should be applied to the data read from the buffer if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 28 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the side-by-side format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access one buffer in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer, and the second display module 1604 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. As shown in FIG. 28, the scan line data of a scan line read from the first input picture and the scan line data of a scan line read from the second input picture are mixed to form one scan line which is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. In this way, the first display module 1602 obtains a first video data and the second display module 1604 obtains a second video data due to the repeated read operation for retrieving the partial scan line data. Please note that scaling should be properly applied to the data read from the buffer if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access one buffer in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer and reading data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Similarly, the scan line data of a scan line read from the first input picture and the scan line data of a scan line read from the second input picture are mixed to form one scan line which is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. Similarly, scaling should be applied to the data read from the buffer if necessary. In this way, the display module 1702 obtains a first video data and a second video data due to the repeated read operation for retrieving the scan line data. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 29 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the side-by-side format. In a first exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access one buffer in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer, and the second display module 1604 is enabled to read data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. In one implementation, the scan line data of an odd scan line read from the first input picture is transmitted during a time period between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display, and the scan line data of an even scan line read from the second input picture is transmitted during the next time period between two successive pulses of the horizontal synchronization signal H-sync. Because of the alternate transmission of the scan line data read from the first input picture and the scan line data read from the second input picture under the control of the properly generated horizontal synchronization signal H-sync, the video output S_OUT with the desired line-by-line format is generated. Specifically, the first display module 1602 obtains a first video data and the second display module 1604 obtains a second video data due to the repeated read operation for retrieving the scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In addition, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. The first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
In a second exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access one buffer in each data scanning clock period. Therefore, during a data scanning clock period, the display module 1702 is enabled to perform a random access for reading data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer and reading data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer. Similarly, the scan line data of an odd scan line read from the first input picture and the scan line data of an even scan line read from the second input picture are respectively transmitted during successive time periods each between two successive pulses of the horizontal synchronization signal H-sync referenced for actual video display. In this way, the display module 1702 obtains a first video data and a second video data due to the repeated read operation for retrieving the scan line data. It should be noted that scaling should be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
FIG. 49 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format. In this exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is also enabled to read data stored in the same buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. It should be noted that scaling may be applied to the data read from the buffer if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. As shown in FIG. 49, the first display module 1602 obtains the first video data with a plurality of black areas distributed therein, wherein each black area (i.e., a crossed-out area marked by “X”) includes pixels each having no effect on the mixed picture. Similarly, the second display module 1604 obtains the second video data with a plurality of black areas distributed therein, wherein each black area (i.e., a crossed-out area marked by “X”) includes pixels each having no effect on the mixed picture. The first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data should be properly mixed to thereby generate the video output S_OUT with the desired checker sampling format as shown in FIG. 49. Please note that the black areas have no dominant effect on the mixed result (i.e., the video output S_OUT) in this embodiment, and may have any pixel values.
FIG. 50 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format. In this exemplary embodiment, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1600 shown in FIG. 16, where the first display module 1602 and the second display module 1604 can simultaneously access different buffers in one data scanning clock period. Therefore, during a data scanning clock period, the first display module 1602 is enabled to read data from a buffer in which a first input picture (e.g., the left-eye picture of the video input S_IN′) is stored and accordingly obtain a first video data; in addition, during the same data scanning clock period, the second display module 1604 is also enabled to read data stored in the same buffer in which a second input picture (e.g., the right-eye picture of the video input S_IN′) is stored and accordingly obtain a second video data. It should be noted that scaling may be applied to the data read from the buffers if necessary. In this embodiment, the data scanning clock period may be equal to a time period between two successive pulses of the vertical synchronization signal V-sync referenced for actual video display. Next, the first display module 1602 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and the second display module 1604 generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first video data and the second video data should be properly multiplexed to thereby generate the video output S_OUT with the desired checker sampling format. For example, the first display module 1602 and the second display module 1604 obtain the first video data and the second video data according to a slower data rate; however, the first display module 1602 and the second display module 1604 output the first video data and the second video data according to a faster data rate used for multiplexing the output of the first video data and the second video data. For example, in one clock cycle of a reference clock, only the first display module 1602 is allowed to output data; however, in the next clock cycle of the reference clock, only the second display module 1604 is allowed to output data.
FIG. 30 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the line-by-line format. FIG. 31 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the line-by-line format. FIG. 32 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the line-by-line format. FIG. 33 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the line-by-line format. FIG. 51 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format. FIG. 52 is a diagram illustrating another exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format. As mentioned above, the storage arrangement for the video input S_IN′ with the side-by-side format is identical to that of the video input S_IN′ with the line-by-line format. Therefore, a person skilled in the art can readily understand details of the exemplary data scanning operations shown in FIG. 30-FIG. 33 and FIG. 51-FIG. 52 after reading above paragraphs directed to exemplary data scanning operations shown in FIG. 26-FIG. 29 and FIG. 49-FIG. 50. Further description is therefore omitted here for brevity.
FIG. 34 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the frame/field sequential format. FIG. 35 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the top-and-bottom format. FIG. 36 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the side-by-side format. FIG. 37 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the line-by-line format. FIG. 38 is a diagram illustrating an exemplary data scanning operation for generating the video output with the checker sampling format according to the video input with the checker sampling format. FIG. 39 is a diagram illustrating an exemplary data scanning operation for generating the video output with the frame/field sequential format according to the video input with the checker sampling format. FIG. 40 is a diagram illustrating an exemplary data scanning operation for generating the video output with the top-and-bottom format according to the video input with the checker sampling format. FIG. 41 is a diagram illustrating an exemplary data scanning operation for generating the video output with the side-by-side format according to the video input with the checker sampling format. FIG. 42 is a diagram illustrating an exemplary data scanning operation for generating the video output with the line-by-line format according to the video input with the checker sampling format. Regarding these exemplary data scanning operations, the format conversion processing unit 108 shown in FIG. 1 is realized by the format conversion processing unit 1700 shown in FIG. 17, where the display module 1702 is configured to randomly access buffer(s) in each data scanning clock period. Therefore, the display module 1702 is enabled to perform a random access for reading data from a first input picture (e.g., the left-eye picture of the video input S_IN′) stored in a buffer and reading data from a second input picture (e.g., the right-eye picture of the video input S_IN′) stored in the same buffer or another buffer, and accordingly obtains a first video data and a second video data. It should be noted that scaling should be applied to the data read from buffer(s) if necessary. In addition, the display module 1702 generates a first output picture (e.g., a left-eye picture of the video output S_OUT) according to the first video data, and generates a second output picture (e.g., a right-eye picture of the video output S_OUT) according to the second video data, where the first output picture and the second output picture are transmitted during one time period between two successive pulses of the vertical synchronization signal V-sync.
Regarding the exemplary embodiment shown in FIG. 1, the video processing apparatus 100 includes the first detecting unit 102 used for detecting the video format VF of the video input S_IN′ and the second detecting unit 104 used for detecting the display capability DC of the display device. However, in a case where the video input S_IN′ fed into the format conversion processing unit 108 is fixed due to a permanent/immobile video source, the video format VF of the video input S_IN′ is constant and can be known in advance. In one alternative design of the video processing apparatus 100 as shown in FIG. 43, the first detecting unit 102 shown in FIG. 1 is omitted, and the modified format conversion control unit 3406 is arranged to generate the control signal S_C according to a predetermined video format VF′ of the video input S_IN′ and the detected display capability DC determined by the second detecting unit 104. That is, the format conversion control unit 3406 determines whether the video input S_IN′ has a 3D video format or a 2D video format by referring to the predetermined video format VF', determines whether the display device 130 supports a 3D video format or a 2D video format by referring to the detected display capability DC, and accordingly generates the control signal S_C. The format conversion processing unit 108 is controlled by the control signal S_C to generate the video output S_OUT which satisfies the detected display capability according to the video input S_IN′ when the video input S_IN′ does not satisfy the detected display capability. The same objective of generating the video output S_OUT satisfying the display capability of the display device 130 is achieved.
Consider another case where the video processing apparatus 100 is integrated with the display device 130, the display capability DC of the display device 130 is fixed and can be known in advance. In another alternative design of the video processing apparatus 100 as shown in FIG. 44, the second detecting unit 104 shown in FIG. 1 is omitted, and the modified format conversion control unit 3506 is arranged to generate the control signal S_C according to the detected video format VF determined by the first detecting unit 102 and a predetermined display capability DC′ of the display device 130. That is, the format conversion control unit 3506 determines whether the video input S_IN′ has a 3D video format or a 2D video format by referring to the detected video format VF, determines whether the display device 130 supports a 3D video format or a 2D video format by referring to the predetermined display capability DC′, and accordingly generates the control signal S_C. The format conversion processing unit 108 is controlled by the control signal S_C to generate the video output S_OUT which satisfies the predetermined display capability according to the video input S_IN′ when the video input S_IN′ does not satisfy the predetermined display capability. The same objective of generating the video output S_OUT satisfying the display capability of the display device 130 is achieved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
