Patents by Inventor Hung H. Tran
Hung H. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10892743Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: February 25, 2019Date of Patent: January 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20190190506Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: February 25, 2019Publication date: June 20, 2019Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10291217Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: March 13, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 10236344Abstract: A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.Type: GrantFiled: October 20, 2015Date of Patent: March 19, 2019Assignee: International Business Machines CorporationInventors: Emre Alptekin, Hung H. Tran, Reinaldo A. Vega, Xiaobin Yuan
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Patent number: 10103226Abstract: A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.Type: GrantFiled: April 30, 2012Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Reinaldo A. Vega, Emre Alptekin, Hung H. Tran, Xiaobin Yuan
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Patent number: 10038468Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: August 8, 2017Date of Patent: July 31, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9954487Abstract: A method for controlling a semiconductor circuit, including forming an inductor and a capacitor on a substrate, which are inductively coupled to one another. The inductor has an inductance value while the capacitor has a capacitance value. The inductor and capacitor make up an oscillator circuit with two terminals. Eddy currents are generated through the capacitor when an operating current flows along the inductor. These eddy currents influence, by inductive coupling, the inductance value and performance of the oscillator circuit, thus simultaneously tuning the inductance and capacitance of the oscillator circuit.Type: GrantFiled: October 7, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhenxing Bi, Hung H. Tran, Zheng Xu
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Publication number: 20180102738Abstract: A method for controlling a semiconductor circuit, including forming an inductor and a capacitor on a substrate, which are inductively coupled to one another. The inductor has an inductance value while the capacitor has a capacitance value. The inductor and capacitor make up an oscillator circuit with two terminals. Eddy currents are generated through the capacitor when an operating current flows along the inductor. These eddy currents influence, by inductive coupling, the inductance value and performance of the oscillator circuit, thus simultaneously tuning the inductance and capacitance of the oscillator circuit.Type: ApplicationFiled: October 7, 2016Publication date: April 12, 2018Inventors: Zhenxing Bi, Hung H. Tran, Zheng Xu
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Publication number: 20170331510Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: August 8, 2017Publication date: November 16, 2017Inventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9748927Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: September 8, 2016Date of Patent: August 29, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9712144Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: September 3, 2015Date of Patent: July 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170187363Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9628059Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: GrantFiled: June 18, 2015Date of Patent: April 18, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9577607Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: August 3, 2015Date of Patent: February 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier Andrea Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170040975Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: September 8, 2016Publication date: February 9, 2017Inventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Publication number: 20170040974Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: ApplicationFiled: August 3, 2015Publication date: February 9, 2017Inventors: Pier Andrea Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan
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Patent number: 9559162Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.Type: GrantFiled: June 19, 2013Date of Patent: January 31, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Jr., Ze Zhang
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Publication number: 20160373099Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: June 18, 2015Publication date: December 22, 2016Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Publication number: 20160373100Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.Type: ApplicationFiled: September 3, 2015Publication date: December 22, 2016Inventors: Mangal Prasad, Marshall D. Tiner, Hung H. Tran, Xiaobin Yuan
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Patent number: 9509281Abstract: Embodiments relate to peaking inductor array for a peaking control unit of a transceiver. An aspect includes the peaking inductor array comprising a plurality of cells connected in parallel, each cell comprising a respective active inductor. Another aspect includes each of the plurality of cells further comprising a decoupling capacitor.Type: GrantFiled: March 28, 2016Date of Patent: November 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pier A. Francese, Mangal Prasad, Hung H. Tran, Xiaobin Yuan