Patents by Inventor Hung H. Tran
Hung H. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9337088Abstract: An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.Type: GrantFiled: June 12, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: William F. Clark, Jr., Robert R. Robison, Hung H. Tran
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Publication number: 20160125115Abstract: An electromagnetic parameterized cell (EM Pcell) is generated for a local environment of an integrated circuit (IC) design for an electronic design flow. A set of parasitics extracted netlists is developed from a set of Pcell layouts and an external EM environment. The parasitics extracted netlists are simulated to provide a set of performance metrics. When a symbolic view of the EM Pcell is displayed to a designer during a subsequent schematic phase of the design flow, the performance metrics are accessed from a design library, to increase accuracy of parameter value selection for the EM Pcell without a parasitics extraction of the physical layout and generation of a parasitics extracted netlist.Type: ApplicationFiled: November 5, 2014Publication date: May 5, 2016Inventors: Sue E. Strang, Hung H. Tran, Wayne H. Woods, JR., Ze Zhang
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Publication number: 20160043175Abstract: A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Emre Alptekin, Hung H. Tran, Reinaldo A. Vega, Xiaobin Yuan
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Publication number: 20150364398Abstract: An semiconductor structure, method of fabrication therefor, and design structure therefor is provided. A thermal grid is formed over at least a portion of a substrate. An insulating layer is formed over at least a portion of the thermal grid. A resistor is formed over at least a portion of the insulating layer. A buried interconnect is connected to the thermal grid via at least one contact. The buried interconnect is adapted to receive thermal energy from the thermal grid via the at least one contact.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: William F. Clark, JR., Robert R. Robison, Hung H. Tran
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Patent number: 9087717Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.Type: GrantFiled: November 26, 2014Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Jr., Ze Zhang
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Patent number: 9058460Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.Type: GrantFiled: March 1, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Douglas M. Daley, Wolfgang Sauter, Hung H. Tran, Wayne H. Woods, Ze Zhang
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Patent number: 8975123Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.Type: GrantFiled: July 9, 2013Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
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Publication number: 20150014633Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.Type: ApplicationFiled: July 9, 2013Publication date: January 15, 2015Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
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Publication number: 20140376595Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, JR., Ze Zhang
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Patent number: 8871576Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.Type: GrantFiled: February 28, 2011Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao
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Patent number: 8866266Abstract: A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.Type: GrantFiled: November 6, 2013Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao
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Publication number: 20140246757Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas M. Daley, Wolfgang Sauter, Hung H. Tran, Wayne H. Woods, Ze Zhang
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Publication number: 20140061583Abstract: A nanotubular MOSFET device extends a scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.Type: ApplicationFiled: November 6, 2013Publication date: March 6, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao
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Publication number: 20130285138Abstract: A method of manufacturing a tunnel field effect transistor (TFET) includes forming on a substrate covered by an epitaxially grown source material a dummy gate stack surrounded by sidewall spacers; forming doped source and drain regions followed by forming an inter-layer dielectric surrounding the sidewall spacers; removing the dummy gate stack, etching a self-aligned cavity; epitaxially growing a thin channel region within the self-aligned etch cavity; conformally depositing gate dielectric and metal gate materials within the self-aligned etch cavity; and planarizing the top surface of the replacement metal gate stack to remove the residues of the gate dielectric and metal gate materials.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Reinaldo A. Vega, Emre Alptekin, Hung H. Tran, Xiaobin Yuan
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Publication number: 20120217468Abstract: A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates.Type: ApplicationFiled: February 28, 2011Publication date: August 30, 2012Applicant: International Business Machines CorporationInventors: Daniel Tekleab, Hung H. Tran, Jeffrey W. Sleight, Dureseti Chidambarrao