Patents by Inventor Hung Lu
Hung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240157217Abstract: A golf teaching method and a golf teaching system are provided. The golf teaching method includes: configuring image capturing devices and golf simulator to capture swing images and corresponding simulator data records, when a user performs a golf swing; configuring an expert model that includes expert motion information and corresponding correction suggestion information; configuring a computing device to perform an analysis process on the swing images and the simulator data records to divide the golf swing into user motions according to stages and obtaining records of user motion information corresponding to the plurality of stages, and to compare the user motion information with the corresponding expert motion information in each stage through the expert model, and to provide the corresponding correction suggestion information according to a comparison result; and configuring a user interface to provide the correction suggestion information.Type: ApplicationFiled: April 20, 2023Publication date: May 16, 2024Inventors: CHENG-HUNG TSAI, CHIA-YU JIH, CHIH-CHUNG CHIEN, LI-LIN LU, SHAO-JUN TAN, WEN-FU LAI
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Patent number: 11983475Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.Type: GrantFiled: February 7, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
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Patent number: 11984649Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.Type: GrantFiled: May 6, 2022Date of Patent: May 14, 2024Assignee: PEGATRON CORPORATIONInventors: Kuo-Chi Cheng, Po-Yen Lai, Ping-Hung Lu
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Patent number: 11983479Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.Type: GrantFiled: August 10, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
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Publication number: 20240150433Abstract: Provided herein are mutants of estrogen receptor alpha ligand binding domain (ER-LBD), and chimeric proteins including such mutant ER-LBD. Also provided are methods of modulating transcription and modulating localization of such chimeric proteins.Type: ApplicationFiled: October 5, 2023Publication date: May 9, 2024Inventors: Michelle Elizabeth Hung, Rebecca Tayler Cottman, Russell Morrison Gordley, Gary Lee, Timothy Kuan-Ta Lu, Srinivasaraghavan Kannan, Chandra Shekhar Verma
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Publication number: 20240153787Abstract: Methods and apparatuses for adjusting and controlling conditions within the environment of a workpiece handling module include sensors for detecting humidity and concentration of harmful gasses. Signals generated by these sensors are utilized to generate signals that control the flow of air into the environment and/or the flow of air and gases out of the environment. By controlling the humidity, negative impacts on processes carried out in the environment are avoided. By controlling the gas concentration, exposure of workers to harmful gases is avoided.Type: ApplicationFiled: February 13, 2023Publication date: May 9, 2024Inventors: Jhih-Yu Li, Nai-Han Cheng, Chien-Hung Lu
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Patent number: 11979156Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.Type: GrantFiled: March 21, 2023Date of Patent: May 7, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Yi-Chen Lu, Hsu-Chi Li, Yi-Jan Chen, Boy-Yiing Jaw, Chin-Tang Chuang, Chung-Hung Chen
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Publication number: 20240145377Abstract: Some embodiments relate to an integrated chip including a first metal insulator metal (MIM) capacitor disposed over a substrate. The integrated chip further includes a second MIM capacitor disposed over the substrate. The first MIM capacitor has a first outer sidewall facing a second outer sidewall of the second MIM capacitor. A dielectric structure is arranged over and laterally between the first MIM capacitor and the second MIM capacitor. A base conductive layer is arranged between the first MIM capacitor and the second MIM capacitor and has a substantially flat upper surface. A metal core arranged on the substantially flat upper surface of the base conductive layer.Type: ApplicationFiled: January 5, 2023Publication date: May 2, 2024Inventors: Liang-Shiuan Peng, Chih-Hung Lu
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Publication number: 20240145482Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.Type: ApplicationFiled: December 19, 2022Publication date: May 2, 2024Applicant: AUO CorporationInventors: Ssu-Hui Lu, Chang-Hung Li, Kuo-Yu Huang, Maw-Song Chen
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Publication number: 20240147639Abstract: An electronic device includes a substrate, a side wiring, a protective film, and a first filler. The substrate has a first surface, a second surface, and a side surface connected between the first surface and the second surface. The side wiring is disposed on the substrate and extends from the first surface to the second surface through the side surface. The protective film is disposed on the side wiring. The side wiring is sandwiched between the substrate and the protective film. An edge of the protective film extends beyond a side wall of the side wiring, and the protective film, the side wall of the side wiring, and the substrate define a gap. The first filler is disposed on the protective film and in the gap, wherein the first filler includes a first material and a plurality of particles mixed within the first material.Type: ApplicationFiled: October 4, 2023Publication date: May 2, 2024Applicant: AUO CorporationInventors: Chih-Wen Lu, Fan-Yu Chen, Chun-Yueh Hou, Hsi-Hung Chen
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Publication number: 20240131159Abstract: Provided herein are mutants of estrogen receptor alpha ligand binding domain (ER-LBD), and chimeric proteins including such mutant ER-LBD. Also provided are methods of modulating transcription and modulating localization of such chimeric proteins.Type: ApplicationFiled: October 4, 2023Publication date: April 25, 2024Inventors: Michelle Elizabeth Hung, Rebecca Tayler Cottman, Russell Morrison Gordley, Gary Lee, Timothy Kuan-Ta Lu, Srinivasaraghavan Kannan, Chandra Shekhar Verma
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Publication number: 20240134150Abstract: A lens driving apparatus includes a holder, a cover, a carrier, a first magnet, a coil, a spring, two second magnets and a hall sensor. The holder includes an opening hole. The cover is made of metal material and coupled to the holder. The carrier is movably disposed in the cover, and for coupling to a lens. The first magnet is connected to an inner side of the cover. The coil is wound around an outer side of the carrier, and adjacent to the first magnet. The spring is coupled to the carrier. The second magnets are disposed on one end of the carrier which is toward the holder. The hall sensor is for detecting a magnetic field of any one of the second magnets, wherein the magnetic field is varied according to a relative displacement between the hall sensor and the second magnet which is detected.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Chun-Yi LU, Te-Sheng TSENG, Wen-Hung HSU
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Patent number: 11963300Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.Type: GrantFiled: July 9, 2021Date of Patent: April 16, 2024Assignee: Au Optronics CorporationInventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
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Publication number: 20240109748Abstract: An optical fiber winding machine with full-time tension control function is provided. The machine includes a first wire storage ring, a first tension sensing module, a first revolution plate, a first rotary servo motor, a first moving assembly, a plurality of first docking elements, a plurality of first electrical connection modules, a second wire storage ring, a second tension sensing module, a second revolution plate, a second rotary servo motor, a second moving assembly, a plurality of second docking elements, a plurality of second electrical connection modules, a rotating shaft, an optical fiber winding ring, and a control module.Type: ApplicationFiled: January 7, 2023Publication date: April 4, 2024Inventors: CHING-LU HSIEH, SHIH-JU FAN, HUNG-PIN CHUNG
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Publication number: 20240112842Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.Type: ApplicationFiled: January 10, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Lu, Chien-Hung Liu, Nuo Xu
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20240079485Abstract: A high electron mobility transistor device including a channel layer, a first barrier layer, and a P-type gallium nitride layer is provided. The first barrier layer is disposed on the channel layer. The P-type gallium nitride layer is disposed on the first barrier layer. The first thickness of the first barrier layer located directly under the P-type gallium nitride layer is greater than the second thickness of the first barrier layer located on two sides of the P-type gallium nitride layer.Type: ApplicationFiled: October 27, 2022Publication date: March 7, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Jih-Wen Chou, Chih-Hung Lu, Bo-An Tsai, Zheng-Chang Mu, Po-Hsien Yeh, Robin Christine Hwang
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Patent number: 11923337Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.Type: GrantFiled: August 29, 2019Date of Patent: March 5, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Chi-Ching Ho, Bo-Hao Ma, Yu-Ting Xue, Ching-Hung Tseng, Guan-Hua Lu, Hong-Da Chang
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Patent number: D1017667Type: GrantFiled: September 23, 2022Date of Patent: March 12, 2024Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Wen-Yo Lu, Matthew J. England, Yen-Chi Tsai, Shao-Hung Wang, James Siminoff
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Patent number: D1019655Type: GrantFiled: November 11, 2021Date of Patent: March 26, 2024Assignee: GETAC TECHNOLOGY CORPORATIONInventors: Wei-Sen Lu, Cheng-Hung Chiang