Patents by Inventor Hung-Wen Liu
Hung-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11975329Abstract: An incubation system includes an actuator, a platform, an incubation lid, and a dispenser. The actuator includes a motion disc and a shaft connected to the motion disc. The shaft extends away from the motion disc. The platform is connected to the shaft of the actuator in a manner allowing movement transmission. The platform has a through hole and a thermal conductive plate. One end of the through hole is sealed by the thermal conductive plate. The incubation lid is movably disposed over the platform. The platform is thermal insulating. The incubation lid has an opening allowing fluid communication, and the dispenser suspends over the thermal conductive plate of the platform.Type: GrantFiled: September 8, 2021Date of Patent: May 7, 2024Assignee: LifeOS Genomics CorporationInventors: Timothy Z. Liu, Hung-Wen Chang
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Patent number: 11955554Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.Type: GrantFiled: July 15, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
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Publication number: 20240114810Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.Type: ApplicationFiled: April 20, 2023Publication date: April 4, 2024Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
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Publication number: 20240075895Abstract: Embodiments are disclosed for crash detection on one or more mobile devices (e.g., smartwatch and/or smartphone). In some embodiments, a method comprises: detecting, with at least one processor, a crash event on a crash device; extracting, with the at least one processor, multimodal features from sensor data generated by multiple sensing modalities of the crash device; computing, with the at least one processor, a plurality of crash decisions based on a plurality of machine learning models applied to the multimodal features; and determining, with the at least one processor, that a severe vehicle crash has occurred involving the crash device based on the plurality of crash decisions and a severity model.Type: ApplicationFiled: September 6, 2023Publication date: March 7, 2024Inventors: Vinay R. Majjigi, Sriram Venkateswaran, Aniket Aranake, Tejal Bhamre, Alexandru Popovici, Parisa Dehleh Hossein Zadeh, Yann Jerome Julien Renard, Yi Wen Liao, Stephen P. Jackson, Rebecca L. Clarkson, Henry Choi, Paul D. Bryan, Mrinal Agarwal, Ethan Goolish, Richard G. Liu, Omar Aziz, Alvaro J. Melendez Hasbun, David Ojeda Avellaneda, Sunny Kai Pang Chow, Pedro O. Varangot, Tianye Sun, Karthik Jayaraman Raghuram, Hung A. Pham
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Patent number: 11710702Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.Type: GrantFiled: June 8, 2020Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventor: Hung Wen Liu
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Publication number: 20210384134Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.Type: ApplicationFiled: June 8, 2020Publication date: December 9, 2021Inventor: Hung Wen Liu
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Patent number: 10966797Abstract: An imaging system includes an image generating device and two reflecting mirrors. The image generating device projects a light toward a gravity direction. The two reflecting mirrors are disposed with respect to each other and one of the two reflecting mirrors is disposed with respect to the image generating device. The light projected by the image generating device forms a virtual image through the two reflecting mirrors in sequence.Type: GrantFiled: March 26, 2020Date of Patent: April 6, 2021Assignee: Qisda CorporationInventors: Tsung-Hsun Wu, Ming-Kuen Lin, Hung-Wen Liu
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Publication number: 20200345450Abstract: An imaging system includes an image generating device and two reflecting mirrors. The image generating device projects a light toward a gravity direction. The two reflecting mirrors are disposed with respect to each other and one of the two reflecting mirrors is disposed with respect to the image generating device. The light projected by the image generating device forms a virtual image through the two reflecting mirrors in sequence.Type: ApplicationFiled: March 26, 2020Publication date: November 5, 2020Inventors: Tsung-Hsun Wu, Ming-Kuen Lin, Hung-Wen Liu
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Publication number: 20170236783Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Patent number: 9666536Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: GrantFiled: December 2, 2015Date of Patent: May 30, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Patent number: 9607974Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: GrantFiled: November 13, 2015Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Patent number: 9397081Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: October 2, 2015Date of Patent: July 19, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20160190099Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.Type: ApplicationFiled: December 2, 2015Publication date: June 30, 2016Inventors: Yi-Wei Liu, Yan-Heng Chen, Mao-Hua Yeh, Hung-Wen Liu, Yi-Che Lai
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Publication number: 20160141227Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
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Publication number: 20160141281Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: ApplicationFiled: October 2, 2015Publication date: May 19, 2016Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Patent number: 9224646Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.Type: GrantFiled: January 2, 2014Date of Patent: December 29, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Hung-Wen Liu
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Patent number: 9177859Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: GrantFiled: August 29, 2013Date of Patent: November 3, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Publication number: 20140342506Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.Type: ApplicationFiled: January 2, 2014Publication date: November 20, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTDInventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Hung-Wen Liu
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Publication number: 20140332976Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.Type: ApplicationFiled: August 29, 2013Publication date: November 13, 2014Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
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Patent number: 8828796Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.Type: GrantFiled: November 20, 2013Date of Patent: September 9, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chieh-Yuan Chi, Wei-Yu Chen, Hung-Wen Liu, Yan-Heng Chen, Hsi-Chang Hsu