Abstract: A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.

Abstract: Disclosed is a structure of a downlink common channel for transmitting an ACK/NACK to notify whether retransmission should be performed through a transmission position of the downlink common channel according to a channel code of a time slot allocated to a UE, and a method for distinguishing an ACK from a NACK, in using a HARQ scheme for uplink transmission of a TDD CDMA scheme in a 3G mobile communication.

Abstract: A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.

Abstract: A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

Abstract: A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Abstract: The present invention relates to a 2,7-carbazole-containing polymer represented by formula 1 and an organic photovoltaic device comprising the conductive polymer as a photoelectric conversion material. The conductive polymer has high photon absorption efficiency and improved hole mobility and is prepared by introducing a specific amount of a carbazole compound either into a polymer, consisting only of a donor functional group containing one or more aromatic monomers, or into a donor-acceptor type polymer comprising a repeating acceptor group introduced into a donor functional group. The conductive polymer can be used as a photoelectric conversion material for organic thin film transistors (OTFTs) or organic light-emitting diodes (OLEDs). Furthermore, the invention provides an organic photovoltaic device comprising the carbazole-containing conductive polymer as an electron donor, and thus can achieve high photoelectric conversion efficiency in organic thin film solar cells.

Abstract: A clock generation circuit includes a plurality of variable delay units configured to control a delay of an input clock signal under the control of delay control signals assigned thereto among a plurality of delay control signals, and output a plurality of delayed clock signals; a phase comparison unit configured to compare a phase of a reference clock signal which has a predetermined phase difference from the input clock signal and a phase of a delayed clock signal which is outputted from any one variable delay unit among the plurality of variable delay units; and a delay control unit configured to generate the plurality of delay control signals based on a comparison result from the phase comparison unit.

Abstract: A clock duty correction circuit includes a first current sourcing unit that sources a current to a current path in response to a clock signal, a first current sinking unit that sinks the current of the current path in response to the clock signal, a second current sourcing unit that sources a current to the current path in response to a delay clock signal obtained by delaying the clock signal by a predetermined time, a second current sinking unit that sinks the current of the current path in response to the delay clock signal, a current adjustment unit that adjusts an amount of the current flowing through the current path according to a voltage level of a control voltage, and a clock output unit that outputs an output clock signal having a voltage level corresponding to the amount of the current flowing through the current adjustment unit.

Abstract: A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Abstract: A delay locked loop (DLL) circuit includes a first feedback loop configured to delay a reference clock signal with a delay line, wherein the first feedback loop is further configured to generate a correction clock signal by correcting a duty cycle of the reference clock signal by adjusting a delay of the delay line; and a second feedback loop configured to generate an output clock signal by detecting a phase of the reference clock signal and delaying the correction clock signal with a delay according to the detection result.

Abstract: A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Abstract: A method for preparing a chalcopyrite-type semiconductor compound which is widely used as a sunlight-absorbing material. More specifically, disclosed is a method for preparing a chalcopyrite-type compound, in which microwaves are used as heat sources in the preparation of the chalcopyrite-type compound, and the chalcopyrite-type compound can be produced in a large amount in a short reaction time using a batch or continuous reactor.

Abstract: A method is provided for performing handover by a terminal in a digital broadcasting system. The method includes measuring strength of a received signal from a serving broadcast transmitter while receiving a broadcast service, and comparing the measured strength of the received signal with a predetermined reference value; periodically measuring strength of the received signal while continuously receiving the broadcast service when the measured strength of the received signal is greater than the reference value; sending a handover start request message for the broadcasting system to a base station of a mobile communication system when the measured strength of the received signal is less than or equal to the reference value; and performing handover from the serving broadcast transmitter to a target broadcast transmitter upon receipt of an accept message for the handover start request for the broadcasting system from the base station.

Abstract: A method for preparing a chalcopyrite-type semiconductor compound which is widely used as a sunlight-absorbing material. More specifically, disclosed is a method for preparing a chalcopyrite-type compound, in which microwaves are used as heat sources in the preparation of the chalcopyrite-type compound, and the chalcopyrite-type compound can be produced in a large amount in a short reaction time using a batch or continuous reactor.

Abstract: A delay locked loop (DLL) of a semiconductor device includes: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second clock signal in synchronization with a second edge of the external clock to output a second delayed clock signal; a duty cycle corrector (DCC) for mixing phases of the first and second delayed clock signals to output a DLL clock signal with a corrected duty cycle; and a DCC controller for disabling the duty cycle corrector in a section during which a phase difference between the first and second delayed clock signals is greater than a preset time after a delay locking.

Abstract: A delay locked loop (DLL) circuit includes a first feedback loop configured to delay a reference clock signal with a delay line, wherein the first feedback loop is further configured to generate a correction clock signal by correcting a duty cycle of the reference clock signal by adjusting a delay of the delay line; and a second feedback loop configured to generate an output clock signal by detecting a phase of the reference clock signal and delaying the correction clock signal with a delay according to the detection result.

Abstract: A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for a delay time to synchronize a clock generated by delaying the source clock for the detected remaining time of the detector with a phase of the source clock.

Abstract: The present inventors show that a brief exposure to EGF stimulates insulin secretion glucose-independently via a Ca2+ influx- and PLD2-dependent mechanism. Furthermore, the present invention shows that EGF is a novel secretagogue that lowers plasma glucose levels in normal and diabetic mice, suggesting the potential for EGF treatment in diabetes.

Abstract: A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time, a second delay line for delaying an inverted version of an output signal from the first delay line by a predetermined amount of time, and a phase mixer for mixing a phase of the output signal from the first delay line and a phase of an output signal from the second delay line and outputting an internal clock having a corrected duty cycle as a result of the mixing.

Abstract: The present invention relates to a blowout for a party including: a blow pipe to which air is introduced; a moving part connected to one side of the blow pipe and having an elastic body mounted along one side surface thereof in such a manner as to elastically spread out and roll by a force of the air supplied from the blow pipe; a switch member disposed at the inside of the blow pipe in such a manner as to be switched to an ‘on’ state if the air is introduced to the blow pipe and to an ‘off’ state if the air blowing stops; and an electronic module connected to the switch member so as to generate an audible sound upon the ‘on’ state of the switch member.