Patents by Inventor Hyong-Ryol Hwang
Hyong-Ryol Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11327838Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.Type: GrantFiled: April 19, 2019Date of Patent: May 10, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung-Hwan Park, Tae-Young Oh, Hyung-Joon Chi, Kyung-Soo Ha, Hyong-Ryol Hwang
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Patent number: 10762947Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.Type: GrantFiled: April 19, 2019Date of Patent: September 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Keon Lee, Kyung-Soo Ha, Hyong-Ryol Hwang
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Patent number: 10671319Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.Type: GrantFiled: June 18, 2018Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jun Shin, Hyong-ryol Hwang
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Publication number: 20200111523Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.Type: ApplicationFiled: April 19, 2019Publication date: April 9, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Keon LEE, Kyung-Soo Ha, Hyong-Ryol Hwang
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Publication number: 20190324854Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.Type: ApplicationFiled: April 19, 2019Publication date: October 24, 2019Inventors: Jung-hwan Park, Tae-young Oh, Hyung-joon Chi, Kyung-soo Ha, Hyong-ryol Hwang
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Publication number: 20190138245Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.Type: ApplicationFiled: June 18, 2018Publication date: May 9, 2019Inventors: Seung-jun SHIN, Hyong-ryol HWANG
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Patent number: 9015389Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.Type: GrantFiled: September 19, 2013Date of Patent: April 21, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Woong Lee, Hyong-Ryol Hwang
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Patent number: 8710591Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.Type: GrantFiled: August 25, 2010Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-ryol Hwang, Ho-cheol Lee, Byong-wook Na
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Publication number: 20140089577Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.Type: ApplicationFiled: September 19, 2013Publication date: March 27, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-Woong LEE, Hyong-Ryol HWANG
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Patent number: 8120986Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: GrantFiled: May 24, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Publication number: 20110095373Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.Type: ApplicationFiled: August 25, 2010Publication date: April 28, 2011Inventors: Hyong-ryol HWANG, Ho-cheol Lee, Byong-wook Na
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Publication number: 20100232249Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Publication number: 20100232213Abstract: Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal.Type: ApplicationFiled: February 24, 2010Publication date: September 16, 2010Inventors: Hyong-Ryol Hwang, Chi-Sung Oh, Sang-Kyu Kang
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Patent number: 7613063Abstract: A method and circuit are disclosed for generating an internal power voltage in a semiconductor memory device. The method includes receiving an external power voltage in an internal power voltage generating circuit and activating a power-up signal during a first period in the applied external power voltage rising to a desired level, powering-up the internal power voltage in relation to the external power voltage during the first period, and continuing the power-up of the internal power voltage during a second period following the first period, the second period extending beyond the deactivation of the power-up signal until receipt of an active command signal.Type: GrantFiled: December 28, 2006Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Ryol Hwang, Ki-Ho Jang
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Patent number: 7606982Abstract: A semiconductor memory device including a plurality of ports, at least one shared memory region of a memory cell array accessible through the ports, and a data transmission controller coupled to the shared memory region and the ports. The data transmission controller is configured to apply a read command of a read operation to the shared memory region after a write command of a write operation before applying any other commands to the shared memory region when at least a portion of a write address associated with the write operation and at least a portion of a read address associated with the read operation are substantially equivalent.Type: GrantFiled: August 22, 2006Date of Patent: October 20, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Ryol Hwang, Sang-Kyun Park
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Publication number: 20090175114Abstract: A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: ApplicationFiled: March 11, 2009Publication date: July 9, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam-Jong KIM, Ho-Cheol LEE, Kyoung-Hwan KWON, Hyong-Ryol HWANG, Hyo-Joo AHN
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Patent number: 7505353Abstract: A multi-port semiconductor memory device having variable access paths and a method therefore are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports.Type: GrantFiled: August 22, 2006Date of Patent: March 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jong Kim, Ho-Cheol Lee, Kyoung-Hwan Kwon, Hyong-Ryol Hwang, Hyo-Joo Ahn
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Patent number: 7492647Abstract: A voltage generation circuit and semiconductor memory device including the same are provided.Type: GrantFiled: February 4, 2008Date of Patent: February 17, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Ryol Hwang, Young-Hyun Jun
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Patent number: 7349268Abstract: A voltage generation circuit and semiconductor memory device including the same are provided.Type: GrantFiled: December 2, 2005Date of Patent: March 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Ryol Hwang, Young-Hyun Jun
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Patent number: 7333387Abstract: I claim a device and method for selecting 1-row and 2-row activation. A device includes a memory block array including a plurality of memory blocks arranged in a row-column format, a plurality of local inter-connectors to selectively couple upper local lines to lower local lines in corresponding rows of memory blocks and a plurality of local-to-global connection points to selectively couple the upper and lower local lines to one or more global lines in at least an upper left block area and a lower right block area of the memory block array, or in a lower left block area and an upper right block area of the memory block array.Type: GrantFiled: July 3, 2006Date of Patent: February 19, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Hyong-Ryol Hwang