Abstract: Disclosed are a coating apparatus and a coating method. The coating apparatus includes a chamber, a support located in an interior space of the chamber and configured to support a substrate which is to be coated, an ejection nozzle configured to eject a coating material toward the support, and an electric field forming unit configured to form an electric field in a movement path of the coating material to provide kinetic energy for the coating material.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.

Abstract: The present invention relates to a cell membrane-mimicking brush polymer having surface properties mimicking a cell membrane and a self-assembly capability by means of a cell membrane mimicking functional group introduced to a brush terminal, and a method for preparing same.

Abstract: A method for communicating data by an electronic device is provided. The method includes transmitting a signal including audio/video (A/V) data to a first external electronic device through a first communication module, while connected with the first external electronic device, generating data or a signal unrelated to the A/V data or receiving the data or signal unrelated to the A/V data from an external electronic device other than the first external electronic device, and providing an audio or a video through a display or an embedded sound device based on at least a portion of the data or the signal unrelated to the A/V data or transmitting the at least a portion of the data or the signal unrelated to the A/V data to a second external electronic device through a second communication module.

Abstract: A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.

Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.

Abstract: A method for communicating data by an electronic device is provided. The method includes transmitting a signal including audio/video (A/V) data to a first external electronic device through a first communication module, while connected with the first external electronic device, generating data or a signal unrelated to the A/V data or receiving the data or signal unrelated to the A/V data from an external electronic device other than the first external electronic device, and providing an audio or a video through a display or an embedded sound device based on at least a portion of the data or the signal unrelated to the A/V data or transmitting the at least a portion of the data or the signal unrelated to the A/V data to a second external electronic device through a second communication module.

Abstract: A method for operating an electronic device according to an embodiment of the present invention may comprise: if an occurrence of a notification is detected, determining an application related to the notification or a keyword extractable from the notification; determining whether feedback of a user for the notification occurs; and storing preference information of the user for the application or the keyword based on the feedback. Also, other embodiments are possible.

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

Abstract: A memory device includes: a memory cell array including a security region configured to store security data; and a security management circuit configured to store a guard key and, responsive to receiving a data operation command for the security region, limit a data operation for the security region by comparing the guard key with an input password that is received by the memory device.

Abstract: The present invention relates to a method for modifying the surface of a polymer substrate. Specifically, the present invention provides a method for modifying the surface of a polymer substrate using a plasma treatment, a hydrophilic primer and a coating agent including a hydrophobic fluorine compound.

Abstract: A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

Abstract: A task mapping method of a NoC semiconductor device includes assigning a first task of a plurality of tasks for node control of the NoC semiconductor device to a first node of a first chip; computing tag values of second tasks of the plurality of tasks which are not assigned to the first node; and assigning the second tasks to a second node according to the tag values.

Abstract: Disclosed are an apparatus and a method for cleaning a component of a substrate dry processing apparatus. The method for cleaning a component of a substrate dry processing apparatus includes dipping the component in a cleaning solution received in a cleaning bath, generating radicals from the cleaning solution, and cleaning the component with the radicals. The component is cleaned with hydrogen radicals (H2*) and hydroxyl radicals (OH*) generated from ozone water. Accordingly, it is possible to rapidly remove carbon (C) and fluorine (F) deposited on the component.