Abstract: A pellicle for extreme ultraviolet lithography has an extreme ultraviolet transmittance of 90% or more and also has thermal stability, mechanical stability, and chemical durability. The pellicle includes a support layer and a pellicle layer. The support layer has an opening formed in a central portion thereof. The pellicle layer is formed on the support layer to cover the opening and includes ZrBx (2<x<16).

Abstract: A nanoscale thin film structure and implementing method thereof, and, more specifically, a nanoscale thin film structure of which target structure is designed with quantized thickness, and a method to implement the nanoscale thin film structure by which the performance of the manufactured nanodevice can be implemented the same as the designed performance, thereby applicable to high sensitivity high performance electronic/optical sensor devices.

Abstract: A method for optimizing a batch size for an artificial neural network accelerator that processes at least one batch in an apparatus for optimizing a batch size is provided. The method for optimizing a batch size includes: receiving information from an artificial neural network to determine a batch size; and determining the batch size for optimizing basic performance of the artificial neural network according to the artificial neural network.

Abstract: This application relates to a method for manufacturing a pellicle for extreme ultraviolet lithography. In one aspect, the method includes forming a support layer of a silicon nitride material on a silicon substrate, and forming a core layer of a graphene material on the support layer. The method may also include forming a graphene defect healing layer on the core layer by selectively forming a material of MeOxNy (Me is one of Si, Al, Ti, Zr, and Hf, x+y=2) at a grain boundary of the core layer in an atomic layer deposition process using heat in order to heal defects generated in graphene forming the core layer without additional damage to the graphene. The method may further include a capping layer on the graphene defect healing layer, wherein a central portion of the silicon substrate under the support layer is removed to form an opening partially exposing the support layer.

Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.

Abstract: This application relates to a method for direct growth of multilayer graphene used as a core layer of a pellicle for extreme ultraviolet lithography. This application also relates to a method for manufacturing the pellicle for extreme ultraviolet lithography by using the multilayer graphene direct growth method. The multilayer graphene direct growth method may include forming few-layer graphene on a silicon nitride substrate, forming a metal catalyst layer on the few-layer graphene, and forming an amorphous carbon layer on the metal catalyst layer. The method may also include directly growing multilayer graphene from the few-layer graphene used as a seed layer by interlayer exchange between the metal catalyst layer and the amorphous carbon layer through heat treatment.

Abstract: A pellicle for extreme ultraviolet lithography has an extreme ultraviolet transmittance of 90% or more and also has thermal stability, mechanical stability, and chemical durability. The pellicle includes a support layer and a pellicle layer. The support layer has an opening formed in a central portion thereof. The pellicle layer is formed on the support layer to cover the opening and includes ZrBx (2<x<16).

Abstract: An apparatus for automatically generating instructions for an artificial intelligence processor and a method for optimizing the same are provided. The method includes: obtaining a combination of conditions for actions performed by the artificial intelligence processor in consideration of optimization condition information for the actions based on model optimization information that optimizes a neural network model to which the artificial intelligence processor is applied and configuration information of the artificial intelligence processor; generating hardware modeling based on the combination of conditions and predicting a performance value through the hardware modeling; and determining an optimal combination of conditions by comparing the predicted performance value and a preset optimal performance value.

Abstract: The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.

Abstract: A neural network accelerator in which processing elements are configured in a systolic array structure includes a memory to store a plurality of feature data including first and second feature data and a plurality of kernel data including first and second kernel data, a first processing element to perform an operation based on the first feature data and the first kernel data and output the first feature data, a selection circuit to select one of the first feature data and the second feature data, based on a control signal, and output the selected feature data, a second processing element to perform an operation based on the selected feature data and one of the first and the second kernel data, and a controller to generate the control signal, based on a neural network characteristic associated with the plurality of feature data and kernel data.

Abstract: Provided is a neural network computing device including a neural network memory configured to store input data, a kernel memory configured to store kernel data corresponding to the input data, a kernel data controller configured to determine whether or not a first part of the kernel data matches a predetermined bit string, and if the first part matches the predetermined bit string, configured to generate a plurality of specific data based on a second part of the kernel data, and a neural core configured to perform a first operation between one of the plurality of specific data and the input data.

Abstract: A method and an apparatus for generating an address of data for an artificial neural network through steps of: performing an N-dimensional loop operation for generating the address of the data based on predetermined parameters, and generating the address of the data in order according to a predetermined direction are provided.

Abstract: In the present invention, by providing an apparatus for processing a convolutional neural network (CNN), including a weight memory configured to store a first weight group of a first layer, a feature map memory configured to store an input feature map where the first weight group is to be applied, an address generator configured to determine a second position spaced from a first position of a first input pixel of the input feature map based on a size of the first weight group, and determine a plurality of adjacent pixels adjacent to the second position; and a processor configured to apply the first weight group to the plurality of adjacent pixels to obtain a first output pixel corresponding to the first position, a memory space may be efficiently used by saving the memory space.

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.

Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.

Abstract: One aspect of the invention provides a method including: receiving shape information describing a shape of a first space of interest (SOI); receiving location information describing a location of the first SOI; associating the shape information with the location information and a first unique ID to form a first SOI object; receiving second information describing at least one of a shape or a location of a second SOI; associating the second information and a second unique ID to form a second SOI object; and associating the first SOI object with the second SOI object.

Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Abstract: One aspect of the invention provides a method including: receiving shape information describing a shape of a first space of interest (SOI); receiving location information describing a location of the first SOI; associating the shape information with the location information and a first unique ID to form a first SOI object; receiving second information describing at least one of a shape or a location of a second SOI; associating the second information and a second unique ID to form a second SOI object; and associating the first SOI object with the second SOI object.

Abstract: An apparatus and method for skipping fractional motion estimation (FME) in high efficiency video coding (HEVC) are disclosed. The apparatus includes a current sum of absolute differences (SAD) acquisition unit, a redundancy determination unit, and a motion estimation skip unit. The SAD acquisition unit acquires the SAD from an integer motion estimation (IME) unit when the IME unit performs IME on a coding tree block (CTB). The redundancy determination unit determines whether or not the CTB is an estimated redundant block using the current SAD. The motion estimation skip unit provides an FME unit with an FME skip signal of the CTB depending on whether or the CTB is an estimated redundant block.

Abstract: One aspect of the invention provides a method for generating a path. The method includes: storing, in a storing unit, at least one path for each arbitrarily set section; setting, in a path setting unit, a main path from an origination to a destination input from a user and then displaying the main path through a display unit; searching, in a path generating unit, for at least one recommended path for one or more sections corresponding to a theme selected from the user and then displaying a searched recommended path through the display unit; receiving, in an input unit, a selection of one or more recommended paths; and generating, in the path generating unit, a final path based on the selection of one or more recommended paths for the one or more sections.