Patents by Inventor Hyung-Suk Choi
Hyung-Suk Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240124363Abstract: An antiferroelectric and a method for manufacturing an antiferroelectric are disclosed herein. The antiferroelectric may have high permittivity and breakdown voltage by having a PbxLa1-x([Zr1-YSnY]ZTi1-Z) composition. The manufacturing of the antiferroelectric may be performed through appropriate mixing and dysprosium addition.Type: ApplicationFiled: July 26, 2023Publication date: April 18, 2024Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, KOREA INSTITUTE OF CERAMIC ENGINEERING AND TECHNOLOGYInventors: Hyung Suk Kim, Hyo Soon Shin, Dong Hun Yeo, Jeoung Sik Choi
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Publication number: 20240055678Abstract: The present disclosure provides a temperature measurement apparatus comprising: a light collecting unit located in at least a partial area of one surface of at least one battery cell, and for collecting electromagnetic waves radiated from the at least one battery cell; a light receiver for receiving the collected electromagnetic waves; and a control unit for measuring a temperature of the at least partial area of the one surface of the at least one battery cell on the basis of the received electromagnetic waves.Type: ApplicationFiled: December 21, 2021Publication date: February 15, 2024Inventors: Hyung Suk CHOI, Woo Jung KANG
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Publication number: 20240035904Abstract: A temperature measurement device according to an embodiment of the present invention may be provided in an energy storage device having a plurality of power device modules. The temperature measurement device may comprise a plurality of sensing spots for temperature sensing, wherein the plurality of sensing spots may include: optical fiber cables spaced a regular unit distance apart from each other; and a plurality cable fixing units disposed between the plurality of power device modules to fix the optical fiber cables. The optical fiber cables may comprise: a plurality of inner sections which are placed between the plurality of power device modules and fixed to the cable fixing units; and at least one outer section which connects the plurality of inner sections in series to each other and has a larger length than the unit distance.Type: ApplicationFiled: August 19, 2021Publication date: February 1, 2024Inventors: Hyung Suk CHOI, Soo Hwan HAN
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Patent number: 11224351Abstract: A wearable device is provided. The wearable device according to one embodiment of the present invention includes a body member including a heartbeat sensor, a first band member and a second band member respectively coupled to both ends of the body member, and a flexible battery having a portion accommodated inside the body member and both remaining ends accommodated inside the first band member and the second band member.Type: GrantFiled: April 1, 2016Date of Patent: January 18, 2022Assignee: AMOGREENTECH CO., LTD.Inventors: Hyung-Suk Choi, Seung Yun Rho
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Patent number: 10770542Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.Type: GrantFiled: June 30, 2015Date of Patent: September 8, 2020Assignee: MagnaChip Semiconductor, Ltd.Inventors: Hyung-suk Choi, Hyun-tae Jung, Eungryul Park, Da-soon Lee
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Patent number: 10395972Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.Type: GrantFiled: January 16, 2018Date of Patent: August 27, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
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Publication number: 20180166322Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.Type: ApplicationFiled: January 16, 2018Publication date: June 14, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Da Soon LEE, Hyung Suk CHOI, Jeong Gyu PARK, Gil Ho LEE, Hyun Tae JUNG, Meng An JUNG, Woo Sig MIN, Pil Seung KANG
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Publication number: 20180132738Abstract: A wearable device is provided. The wearable device according to one embodiment of the present invention includes a body member including a heartbeat sensor, a first band member and a second band member respectively coupled to both ends of the body member, and a flexible battery having a portion accommodated inside the body member and both remaining ends accommodated inside the first band member and the second band member.Type: ApplicationFiled: April 1, 2016Publication date: May 17, 2018Applicant: AMOGREENTECH CO., LTD.Inventors: Hyung-Suk CHOI, Seung Yun RHO
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Patent number: 9922865Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.Type: GrantFiled: October 30, 2013Date of Patent: March 20, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
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Publication number: 20150303253Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.Type: ApplicationFiled: June 30, 2015Publication date: October 22, 2015Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Hyung-suk CHOI, Hyun-tae JUNG, Eungryul PARK, Da-soon LEE
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Patent number: 9105684Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.Type: GrantFiled: May 7, 2012Date of Patent: August 11, 2015Assignee: Magnachip Semiconductor, Ltd.Inventors: Hyung-suk Choi, Hyun-tae Jung, Eung-ryul Park, Da-soon Lee
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Patent number: 9099557Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: GrantFiled: September 26, 2013Date of Patent: August 4, 2015Assignee: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8969161Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: GrantFiled: October 3, 2013Date of Patent: March 3, 2015Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8853787Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.Type: GrantFiled: November 30, 2012Date of Patent: October 7, 2014Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20140291767Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating film on a side surface of the deep trench; an interlayer insulating film on the sidewall insulating film; and an air gap in the interlayer insulating film.Type: ApplicationFiled: October 30, 2013Publication date: October 2, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Da Soon Lee, Hyung Suk Choi, Jeong Gyu Park, Gil Ho Lee, Hyun Tae Jung, Meng An Jung, Woo Sig Min, Pil Seung Kang
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Publication number: 20140151793Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end portion thereof extending over the isolation layer.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Patent number: 8716796Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: August 1, 2013Date of Patent: May 6, 2014Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8692328Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: August 1, 2013Date of Patent: April 8, 2014Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20140030862Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: ApplicationFiled: October 3, 2013Publication date: January 30, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Publication number: 20140027846Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH