Patents by Inventor Hyung-Suk Choi
Hyung-Suk Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140021541Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: August 1, 2013Publication date: January 23, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, IN-Taek OH
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Publication number: 20140021542Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: August 1, 2013Publication date: January 23, 2014Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, In-Taek OH
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Patent number: 8575702Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: GrantFiled: September 15, 2010Date of Patent: November 5, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8552497Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: GrantFiled: November 7, 2011Date of Patent: October 8, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8546881Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: GrantFiled: September 2, 2010Date of Patent: October 1, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8546883Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: GrantFiled: July 13, 2010Date of Patent: October 1, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20130075857Abstract: An isolation structure of a semiconductor, a semiconductor device having the same, and a method for fabricating the isolation structure are provided. An isolation structure of a semiconductor device may include a trench formed in a substrate, an oxide layer formed on a bottom surface and an inner sidewall of the trench, a filler formed on the oxide layer to fill a part of inside of the trench, and a fourth oxide layer filling an upper portion of the filler of the trench to a height above an upper surface of the trench, an undercut structure being formed on a boundary area between the inner sidewall and the oxide layer.Type: ApplicationFiled: May 7, 2012Publication date: March 28, 2013Inventors: Hyung-suk CHOI, Hyun-tae Jung, Eung-ryul Park, Da-soon Lee
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Patent number: 8362556Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end; portion thereof extending over the isolation layer.Type: GrantFiled: July 13, 2010Date of Patent: January 29, 2013Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 8131153Abstract: A communication equipment which is utilized in a power line communication (PLC) system utilizing a hybrid fiber coax (HFC) which includes a PLC optical network unit, a PLC trunk bridge amplifier, a PLC distribution amplifier, and a PLC coupling device. In this instance, the PLC optical network unit does not require a PLC protocol conversion of an Ethernet signal by a cable modem and a PLC modem in each subscriber location, and enables a PLC communication between the each subscriber location and a communication terminal utilizing a PLC Ethernet signal as is, by receiving an optical signal from an optical transmitter via an optical fiber, converting the optical signal into the PLC Ethernet signal corresponding to a predetermined PLC protocol, and transmitting the PLC Ethernet signal to at least one subscriber location via a coaxial cable.Type: GrantFiled: November 29, 2006Date of Patent: March 6, 2012Assignee: LS Cable Ltd.Inventors: Dong Young Park, Kwan Hee Han, Sung Wook Moon, Hyung Suk Choi, Wan Yoon Lee
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Publication number: 20120049278Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: ApplicationFiled: November 7, 2011Publication date: March 1, 2012Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young CHAE, In-Taek OH
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Patent number: 8076726Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: GrantFiled: July 14, 2010Date of Patent: December 13, 2011Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20110133279Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.Type: ApplicationFiled: July 14, 2010Publication date: June 9, 2011Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20110133277Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.Type: ApplicationFiled: September 2, 2010Publication date: June 9, 2011Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20110127612Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.Type: ApplicationFiled: September 15, 2010Publication date: June 2, 2011Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-Goo Kim, Hyung-Suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Publication number: 20110115020Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.Type: ApplicationFiled: July 13, 2010Publication date: May 19, 2011Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han CHA, Kyung-Ho LEE, Sun-Goo KIM, Hyung-Suk CHOI, Ju-Ho KIM, Jin-Young Chae, In-Taek OH
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Publication number: 20110115016Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end ;portion thereof extending over the isolation layer.Type: ApplicationFiled: July 13, 2010Publication date: May 19, 2011Applicant: MAGNACHIP SEMICONDUCTOR, LTD.Inventors: Jae-Han Cha, Kyung-Ho Lee, Sun-goo Kim, Hyung-suk Choi, Ju-Ho Kim, Jin-Young Chae, In-Taek Oh
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Patent number: 7853720Abstract: A method and system can access local network access devices whose IP (Internet Protocol) addresses are not registered to a DNS (Domain Name System) server using domain names. For this, a local network gateway registers the IP addresses and the domain names mapped to the IP addresses thereto. If a domain name contained in a received DNS query packet is registered to the local network gateway, the local network gateway changes a DNS query packet into a DNS answer packet containing an IP address corresponding to the registered domain name and then transmits the DNS answer packet to a local personal computer. Otherwise, the local network gateway passes the DNS query packet to an external network as it is.Type: GrantFiled: April 21, 2003Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Suk Choi, Bo-Gu Lee, Yong-Moon Won
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Publication number: 20080317472Abstract: A communication equipment which is utilized in a power line communication (PLC) system utilizing a hybrid fiber coax (HFC) which includes a PLC optical network unit, a PLC trunk bridge amplifier, a PLC distribution amplifier, and a PLC coupling device. In this instance, the PLC optical network unit does not require a PLC protocol conversion of an Ethernet signal by a cable modem and a PLC modem in each subscriber location, and enables a PLC communication between the each subscriber location and a communication terminal utilizing a PLC Ethernet signal as is, by receiving an optical signal from an optical transmitter via an optical fiber, converting the optical signal into the PLC Ethernet signal corresponding to a predetermined PLC protocol, and transmitting the PLC Ethernet signal to at least one subscriber location via a coaxial cable.Type: ApplicationFiled: November 29, 2006Publication date: December 25, 2008Inventors: Dong Young Park, Kwan Hee Han, Sung Wook Moon, Hyung Suk Choi, Wan Yoon Lee
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Publication number: 20080279199Abstract: A lock device having a lever is disclosed, in which the lever is released to rotate a latch bolt only if a correct electronic key is authenticated while the latch bolt is hooked over the lever at normal times.Type: ApplicationFiled: November 29, 2006Publication date: November 13, 2008Inventors: Dong Young Park, Kwan Hee Han, Sung Wook Moon, Hyung Suk Choi
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Patent number: 7443755Abstract: A fuse box of a semiconductor device is provided. More specifically, provided is a device of forming a uniformly residual oxide film by rearranging fuse boxes in consideration of an etching ratio depending on plasma density of the semiconductor device to prevent a fuse attack. During a repair etching process to open a fuse box in a chip, an etching loading effect is evenly reflected depending on pattern density of the fuse box so that the residual oxide film is regularly distributed in each fuse of all fuse boxes regardless of the size of an open region. As a result, the fuse attack resulting from an excessive etching process on the oxide film on a small fuse is prevented in fuse blowing to improve yield of FTA (Fixed To Attempt) yield.Type: GrantFiled: December 30, 2005Date of Patent: October 28, 2008Assignee: Hynix Semiconductor Inc.Inventor: Hyung Suk Choi