Patents by Inventor Hyunui LEE
Hyunui LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960906Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.Type: GrantFiled: October 21, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventor: Hyunui Lee
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Patent number: 11922996Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.Type: GrantFiled: October 4, 2021Date of Patent: March 5, 2024Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Won Joo Yun
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Patent number: 11848065Abstract: Semiconductor devices are disclosed. A semiconductor device may include a number of impedance calibration circuits and an interpolation circuit. The interpolation circuit may be configured to generate a calibration code based on two or more other calibration codes generated via one or more impedance calibration circuits of the number of impedance calibration circuits, another interpolation circuit, or any combination thereof. Methods and systems are also disclosed.Type: GrantFiled: August 31, 2021Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventor: Hyunui Lee
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Patent number: 11677537Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.Type: GrantFiled: March 17, 2021Date of Patent: June 13, 2023Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Won Joo Yun, Baekkyu Choi
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Patent number: 11670397Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.Type: GrantFiled: April 23, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Masayoshi Yamazaki
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Patent number: 11646073Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.Type: GrantFiled: April 13, 2022Date of Patent: May 9, 2023Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Takamasa Suzuki, Yasuo Satoh, Yuan He
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Publication number: 20230110208Abstract: A semiconductor device may include one or more output drivers. An output driver may be adjusted for impedance matching by applying a body voltage to one or more transistors of the output driver. In some examples, the body voltage applied may be based on a comparison between a reference voltage and a voltage at an external terminal. In some examples, the semiconductor device may include a calibration circuit that includes a comparator and an up/down counter that, based on a signal from the comparator, generates a code indicating the body voltage to be applied. The body voltage may be applied by a voltage generator in some examples.Type: ApplicationFiled: October 4, 2021Publication date: April 13, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: HYUNUI LEE, WON JOO YUN
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Patent number: 11619964Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.Type: GrantFiled: July 26, 2021Date of Patent: April 4, 2023Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Won Joo Yun
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Publication number: 20230062002Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.Type: ApplicationFiled: October 21, 2022Publication date: March 2, 2023Inventor: Hyunui Lee
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Publication number: 20230029528Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.Type: ApplicationFiled: July 26, 2021Publication date: February 2, 2023Inventors: Takehiro Hasegawa, Chikara Kondo, Yuan He, Hyunui Lee
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Publication number: 20230025173Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a command signal according to a clock signal to obtain standard-timing commands. The method may also include sampling the command signal according to an adjusted clock signal to obtain time-adjusted commands. The method may also include comparing the standard-timing commands and the time-adjusted commands. The method may also include determining an improved timing for the clock signal based on the comparison of the standard-timing commands and the time-adjusted commands. The method may also include adjusting the clock signal based on the improved timing. Associated systems and methods are also disclosed.Type: ApplicationFiled: July 26, 2021Publication date: January 26, 2023Inventors: Hyunui Lee, Won Joo Yun
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Patent number: 11494198Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.Type: GrantFiled: January 4, 2021Date of Patent: November 8, 2022Assignee: Micron Technology, Inc.Inventor: Hyunui Lee
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Publication number: 20220343996Abstract: A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration code may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Hyunui Lee, Masayoshi Yamazaki
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Publication number: 20220301610Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Applicant: Micron Technology, Inc.Inventors: Takamasa Suzuki, Yasuo Satoh, Yuan He, Hyunui Lee
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Publication number: 20220303111Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Inventors: Hyunui Lee, Won Joo Yun, Baekkyu Choi
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Patent number: 11443788Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.Type: GrantFiled: March 17, 2021Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Takamasa Suzuki, Yasuo Satoh, Yuan He, Hyunui Lee
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Publication number: 20220246193Abstract: Some embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.Type: ApplicationFiled: April 13, 2022Publication date: August 4, 2022Applicant: Micron Technology, Inc.Inventors: Hyunui Lee, Takamasa Suzuki, Yasuo Satoh, Yuan He
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Patent number: 11398266Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.Type: GrantFiled: January 8, 2021Date of Patent: July 26, 2022Assignee: Micron Technology, Inc.Inventors: Hyunui Lee, Takamasa Suzuki, Yasuo Satoh, Yuan He
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Publication number: 20220223191Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.Type: ApplicationFiled: January 8, 2021Publication date: July 14, 2022Applicant: Micron Technology, Inc.Inventors: Hyunui Lee, Takamasa Suzuki, Yasuo Satoh, Yuan He
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Publication number: 20220214890Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Inventor: Hyunui Lee