Abstract: A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

Abstract: A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

Abstract: Semiconductor devices are disclosed. A semiconductor device may include a number of impedance calibration circuits and an interpolation circuit. The interpolation circuit may be configured to generate a calibration code based on two or more other calibration codes generated via one or more impedance calibration circuits of the number of impedance calibration circuits, another interpolation circuit, or any combination thereof. Methods and systems are also disclosed.

Abstract: Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.

Abstract: Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: An output driver is disclosed. An output driver may include a pre-driver and a main driver coupled to the pre-driver. The main driver may include at least one switch, and a first transistor coupled between a first supply voltage and the at least one switch. The main driver may also include a second transistor coupled between a second, different supply voltage and the at least one switch. The at least one switch is configured to couple an output node of the output driver to one of the first transistor and the second transistor in response to receipt of a control signal. The main driver may also include a third transistor coupled between a reference voltage and the output node. An electronic system including at least one output driver, and methods of operating an output driver are also described.

Abstract: Apparatuses and methods for providing clocks to data paths are disclosed. An example apparatus includes a first circuit in a data path, a second circuit in the data path, and a multiplexer. The first circuit is configured to provide data based on a first clock and the second circuit is configured to receive the data and provide the data based on a second clock. The multiplexer is configured to provide a third clock as the second clock for some test operations and further configured to provide the first clock as the second clock for other test operations. A timing of the first clock is adjusted for the first circuit during the test operations.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: A semiconductor memory device includes first bumps positioned along a first direction; second bumps positioned in parallel to the first bumps along the first direction; first registers connected with the first bumps; and second registers connected with the second bumps. The first registers and the second registers are sequentially connected and form a shift register.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.

Abstract: A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to a first surface of the interposer, and a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to a second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view may be provided.

Abstract: Provided is a memory device configured to perform a calibration operation without having a ZQ pin. The memory device includes a calibration circuit configured to generate a pull-up calibration code and a pull-down calibration code which termination of a data input/output pad for impedance matching in the data input/output pad is controlled. The calibration circuit performs a first calibration operation for trimming first and second reference resistors based on an external resistor to be connected to a pad, and a second calibration operation for generating the pull-up calibration code and the pull-down calibration code based on the trimmed second reference resistor.

Abstract: A memory device including a parity check circuit and a mask circuit may be provided. The parity check circuit may perform parity check on data sampled according to a data strobe signal, which does not include a post-amble. The mask circuit may generate a parity error signal based on results of the parity check, and output the parity error signal during a time period determined according to a burst length of the data.

Abstract: Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.