Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A method of broadcasting event messages in a system-on-chip having system circuitry and monitoring circuitry for monitoring the system circuitry, the monitoring circuitry comprising units connected in a tree-based structure for routing communications through the system-on-chip, the tree-based structure comprising branches extending from a root unit, each branch comprising a plurality of units, each unit connected to a single unit above in the branch and a single unit below in the branch, whereby each unit routes communications to and from individually addressable entities above that unit in its branch, the tree-based structure further comprising crosslinks connecting corresponding units of adjacent branches, the method comprising: if an event is generated at an event unit or its local subsystem, routing an event message directly from that event unit to: any adjacent unit above the event unit in the event unit's branch, any adjacent unit below the event unit in the event unit's branch, and any corresponding un

Abstract: An integrated circuit chip has a set of communication units, each unit being configured to operate according to a protocol in which a data packet sent by one unit is receivable by one unit only, each unit being configured to send at least one packet having one of a plurality of tiers to at least one other unit and being configured to specify, for each tier, a subset of destination units to which packets of that tier are to be sent, wherein each unit is configured to: receive a packet having one of the plurality of tiers; determine the tier of the received packet; and sequentially send packets having a different tier to the tier of the received packet to each of the respective subset of destination units for the different tier.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A communication unit and discoverable unit communicate according to a protocol in which unit addresses are not of a predetermined length. The communication unit sends a discovery request to the discoverable unit. The discoverable unit receives the discovery request and generates a discovery response. The discovery response comprises an address field of length unknown to the communication unit, populated with an address of the discoverable unit. The discovery response also comprises a flag following the address field. The discoverable unit sends the discovery response to the communication unit. The communication unit receives the discovery response and determines the address field length by counting the number of bits prior to the flag.

Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: A method of broadcasting event messages in a system-on-chip having system circuitry and monitoring circuitry for monitoring the system circuitry, the monitoring circuitry comprising units connected in a tree-based structure for routing communications through the system-on-chip, the tree-based structure comprising branches extending from a root unit, each branch comprising a plurality of units, each unit connected to a single unit above in the branch and a single unit below in the branch, whereby each unit routes communications to and from individually addressable entities above that unit in its branch, the tree-based structure further comprising crosslinks connecting corresponding units of adjacent branches, the method comprising: if an event is generated at an event unit or its local subsystem, routing an event message directly from that event unit to: any adjacent unit above the event unit in the event unit's branch, any adjacent unit below the event unit in the event unit's branch, and any corresponding un

Abstract: An integrated circuit chip has a set of communication units, each unit being configured to operate according to a protocol in which a data packet sent by one unit is receivable by one unit only, each unit being configured to send at least one packet having one of a plurality of tiers to at least one other unit and being configured to specify, for each tier, a subset of destination units to which packets of that tier are to be sent, wherein each unit is configured to: receive a packet having one of the plurality of tiers; determine the tier of the received packet; and sequentially send packets having a different tier to the tier of the received packet to each of the respective subset of destination units for the different tier.

Abstract: A processor supervisory unit for monitoring the program flow executed by a processor, the supervisory unit being arranged to store a set of values representing locations to which the program flow is expected to return after jumps in the program flow, the unit being capable of: in a first mode, on detecting a jump in the program flow to store a location value representing a location to which the program flow is expected to return from that jump; and in a second mode, on detecting a jump in the program flow to increment a counter associated with a location value representing a location to which the program flow is expected to return from that jump.

Abstract: A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.

Abstract: A power supply is described having a current measurement circuit connected between a supply voltage terminal and an output voltage terminal of the power supply. The current measurement circuit comprises a set of two or more sense resistors in a parallel configuration, first and second ones of the sense resistors having different impedances. Switching circuitry is provided, which is responsive to a control signal to connect one or more of the sense resistors between the supply voltage terminal and the output voltage terminal. A controller is operable to generate the control signal in dependence on a measured current level across the set of sense resistors. In this way, by switching the resistors in and out of the circuit, the voltage drop across the measurement circuit can be kept to a desired range.

Abstract: A communication unit and discoverable unit communicate according to a protocol in which unit addresses are not of a predetermined length. The communication unit sends a discovery request to the discoverable unit. The discoverable unit receives the discovery request and generates a discovery response. The discovery response comprises an address field of length unknown to the communication unit, populated with an address of the discoverable unit. The discovery response also comprises a flag following the address field. The discoverable unit sends the discovery response to the communication unit. The communication unit receives the discovery response and determines the address field length by counting the number of bits prior to the flag.

Abstract: An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action.

Abstract: A power supply is described having a current measurement circuit connected between a supply voltage terminal and an output voltage terminal of the power supply. The current measurement circuit comprises a set of two or more sense resistors in a parallel configuration, first and second ones of the sense resistors having different impedances. Switching circuitry is provided, which is responsive to a control signal to connect one or more of the sense resistors between the supply voltage terminal and the output voltage terminal. A controller is operable to generate the control signal in dependence on a measured current level across the set of sense resistors. In this way, by switching the resistors in and out of the circuit, the voltage drop across the measurement circuit can be kept to a desired range.

Abstract: An integrated circuit, having a security supervision system, comprising a plurality of functional circuit blocks interconnected to collectively performing data processing tasks, one or more communication adaptors, having: (i) a hardware interconnection to the functional circuit blocks, whereby the communication adaptor senses the state and/or activity of the functional circuit block; (ii) memory storing definitions of state and/or activity of functional circuit block and actions for each definition; and (iii) processing circuitry comparing the state and/or activity of the functional block with each definition, such that when state and/or activity of the functional block corresponding to a stored definition is detected, perform the corresponding action.

Abstract: The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate.