Abstract: In a gas turbine having a chordal hinge seal between an inner rail of each nozzle segment and an annular axially facing sealing surface of a nozzle support ring, a supplemental seal is disposed between the support ring and inner rail of each nozzle segment radially inwardly of the chordal hinge seal. To minimize or prevent leakage flow across the chordal hinge seal, the seal is formed of flexible sheet metal which extends between the inner rail and a seat projecting from the annular sealing surface of the support ring radially inwardly of the chordal hinge seal. A first margin of the flexible seal engages in an arcuate groove carried by the inner rail. The opposite margin extends arcuately in sealing engagement along the seat carried by the nozzle support ring.

Abstract: In a gas turbine having a chordal hinge seal between an inner rail of each nozzle segment and an annular axially facing sealing surface of a nozzle support ring, a supplemental seal is disposed between the support ring and inner rail of the nozzle segment on a high pressure side of the chordal hinge seal. The supplemental seal includes a pair of sheet metal shims overlaid by a woven metallic cloth supported by a bracket secured to a back side surface of the inner rail. The radially inner end of the cloth seal bears against the annular sealing surface of the nozzle support ring. The shims of the legs of the supplemental seal are slit along their distal margin and staggered in a chord-wise direction relative to one another to provide flexibility and effective sealing engagement with the nozzle support ring.

Abstract: An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized direct memory access unit. The external direct memory access controller may update source or destination address for a next occurrence of an event type by adding an offset or updating an address pointer to a linked list. The centralized direct memory access unit queues data transfer parameters on a priority channel basis and stalls the external direct memory access controller for a particular priority level it the corresponding queue is full.

Abstract: An impingement insert sleeve is provided that is adapted to be disposed in a coolant cavity defined through a stator vane. The insert has a generally open inlet end and first and second pairs of diametrically opposed side walls, and at least one fail-safe tab defined at a longitudinal end of the insert for limiting radial displacement of the insert with respect to the stator vane.

Abstract: An impingement insert sleeve is provided that is adapted to be disposed in a coolant cavity defined through a stator vane. The insert has a generally open inlet end and first and second pairs of diametrically opposed side walls, and at least one fail-safe tab defined at a longitudinal end of the insert for limiting radial displacement of the insert with respect to the stator vane.

Abstract: The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.

Abstract: This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchronizer stages each include a data register (601, 602, 603, 604, 605) and a synchronizer circuit (611, 612, 613, 614, 615). The synchronizer circuit synchronizes a first domain write request signal to the second clock signal. A write pointer (625) enables one synchronizer stage to write first domain data upon receipt of said first domain write request signal (321). The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. A read pointer (635) enables an indicated read stage to recall data from the corresponding data register upon output synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence.

Abstract: A turbine bucket includes an airfoil extending from a platform, having high and low pressure sides; a wheel mounting portion; a hollow shank portion located radially between the platform and the wheel mounting portion, the platform having an under surface. An impingement cooling plate is located in the hollow shank portion, spaced from the under surface, and the impingement plate is formed with a plurality of impingement cooling holes therein.

Abstract: The data transfer apparatus and method employs two queue counters to maintain the status of a first-in-first-out buffer memory. A master count (251) indicates the number of entries available for use within the FIFO (410). New data can be allocated to the FIFO only if this master count is non-zero. This master count is decremented (401) upon allocation of new data to the FIFO. A remote count (252) stores the number of data entries stored in the FIFO. This remote count is incremented (413) upon allocation of data to the FIFO and decremented (414) upon reading data from the FIFO. A confirm decrement signal (408) from the remote count triggers an increment of the master count. This two counter technique makes better use of the available bandwidth than the prior art by not requiring a FIFO depth equal the to the data transfer latency. This technique is particularly useful in systems with delays between the data source and data destination and a mismatch of maximum data transfer rates.

Abstract: A data processing apparatus for increasing the speed of data transfer from one processor instruction to another processor instruction. First (78) and second (80) functional unit groups, each including a plurality of functional units, are connected to a register file (76) comprising a plurality of registers having corresponding register numbers. A comparator (181) receives an indication of the operand register number of a current instruction for a functional unit in the first functional unit group, and an indication of the destination register number of an immediately preceding instruction for the second functional unit group, and indicates whether the register numbers match.

Abstract: A method of operating a gas turbine having inner and outer shells, with the inner shell being radially movable relative to rotor bucket tip passage in the inner shell for flowing a thermal medium. A pair of passage portions are formed in each of the aft and forward inner shell sections with axially communicating passageways between the passage portions. A thermal medium, preferably from an off-turbine site, is provided for flow through the second-stage aft inner shell section, along axial passageways along the mid-line of the inner shell to a first passage portion of the forward inner shell section. Cross-over paths flow the thermal medium from the first passage portions to second circumferentially extending passage portions of the forward inner shell section, in turn, in communication with axial passageways extending from the forward section to the aft section. A second pair of passage portions flow the thermal medium to an outlet in the aft section.

Abstract: A gas turbine nozzle segment has outer and inner band portions. Each band portion includes a nozzle wall, a cover and an impingement plate between the cover and nozzle wall defining two cavities on opposite sides of the impingement plate. Cooling steam is supplied to one cavity for flow through the apertures of the impingement plate to cool the nozzle wall. Structural pedestals interconnect the cover and nozzle wall and pass through holes in the impingement plate to reduce localized stress otherwise resulting from a difference in pressure within the chamber of the nozzle segment and the hot gas path and the fixed turbine casing surrounding the nozzle stage. The pedestals may be cast or welded to the cover and nozzle wall.

Abstract: A turbine bucket includes an airfoil extending from a platform, having high and low pressure sides; a wheel mounting portion; a hollow shank portion located radially between the platform and the wheel mounting portion, the platform having an under surface. An impingement cooling plate is located in the hollow shank portion, spaced from the under surface, and the impingement plate is formed with a plurality of impingement cooling holes therein.

Abstract: A turbine shroud cooling cavity is partitioned to define a plurality of cooling chambers for sequentially receiving cooling steam and impingement cooling of the radially inner wall of the shoud. An impingement baffle is provided in each cooling chamber for receiving the cooling media from a cooling media inlet in the case of the first chamber or from the immediately upstream chamber in the case of the second through fourth chambers and includes a plurality of impingement holes for effecting the impingement cooling of the shroud inner wall.

Abstract: Data transfers involving accesses of multiple banks of a DRAM having a shared sense amplifier architecture can be performed while also avoiding bank conflicts and associated data bus latency. Groups of DRAM banks which can be sequentially accessed during a given data transfer without conflicting with one another are identified and utilized for data transfers. Each data transfer sequentially accesses the banks of one of the groups. The sequence in which the banks of a given group will be accessed during a data transfer can advantageously be reordered in order to prevent conflicts with banks that have been or will be accessed during prior or subsequent data transfers. In this manner, consecutive data transfers, each involving accesses to multiple banks of a DRAM having a shared sense amplifier architecture, can be performed without any data bus latency between or within the transfers.

Abstract: A scannable asynchronous preset and/or clear flip-flop having latch circuits 27 and 30. Latch circuit 27 comprises an inverter 28 and a tristate NAND gate 29. Latch circuit 30 comprises an inverter 31 and a tristate NOR gate 32. When the CLK (clock input signal) and CLRZ (the inverse of the clear input signal) are both low, the output of the tristate NOR gate 32 is forced low. Thus the input of inverter 31 is low so that the output signal, Q, is forced low and the inverse output signal, QZ, is forced high. When CLK is high and CLRZ is low the output of tristate NAND gate 29 is forced high so that the input to inverter 28 is high and the input to inverter 31 is low, thereby forcing Q low and QZ high. Thus the outputs Q and QZ are forced low and high respectively when CLRZ is low, regardless of the state of the CLK input.

Abstract: This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchronizer stages each include a data register (601, 602, 603, 604, 605) and a synchronizer circuit (611, 612, 613, 614, 615). The synchronizer circuit synchronizes a first domain write request signal to the second clock signal. a write pointer (625) enables one synchronizer stage to write first domain data upon receipt of said first domain write request signal (321). The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. a read pointer (635) enables an indicated read stage to recall data from the corresponding data register upon output synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence.

Abstract: A network switch system (10) is disclosed, in which a plurality of switch fabric devices (20) are interconnected according to a ring arrangement, each of the switch fabric devices (20) including therein switch interfaces (22) coupled to corresponding network switches (14, 16). Each switch fabric device includes a plurality of ring paths (24), each of which is associated with a receive ring interface (26R) and a transmit ring interface (26X). Each ring path (24) includes a circular buffer (44) having a plurality of entries, each of which is associated with valid logic (50). The valid logic (50) for each entry presents valid signals on valid lines (WV, RV) to the receive and transmit domains of the ring path (24), and receives signals on write and read word request lines (WRW, RDW) therefrom.

Abstract: Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

Abstract: This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories. The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address.