Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

Abstract: A beamforming integrated circuit has a single channel with a transmit chain and a receive chain. The transmit chain is configured to transmit an output signal and, in a corresponding manner, the receive chain is configured to receive an input signal. The integrated circuit also has separate horizontal and vertical polarity ports, and a double pole, double throw switch operably coupled between the chains and the ports. The double pole, double throw switch is configured to switch between operation in a first mode and a second mode.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: In some example implementations, there may be provided methods for beamforming calibration of active electronically steered arrays (AESA). In some implementations, one or more adders may generate a phase offset by adding phase calibration data from non-volatile memory and phase command data from static memory, and/or generate a gain offset by adding gain calibration data from the non-volatile memory and gain command data from the static memory. Further, a phase-shift circuit can modify, based on the phase offset, a phase of a first output signal, and an amplitude gain circuit can modify, based on the gain offset, an amplitude of the first output signal. In accordance with these implementations, the modified phase of the first output signal and the modified amplitude of the first output signal are provided to enable pre-calibration of the first output signal and/or a first antenna. Related systems, methods, and articles of manufacture are also described.

Abstract: A voltage controlled oscillator (VCO) is provided that includes an output buffer having a first buffer stage including a first transistor and a second buffer stage including a second transistor. The first and second transistors are connected in a cascaded emitter follower buffer arrangement.

Abstract: A frequency multiplier is provided that includes a switching component having a plurality of differential pairs of transistors. The frequency multiplier further includes a gain stage. A common mode feedback generated by the switching component is also provided to the gain stage.

Abstract: A tunable transformer providing switched inductance includes a primary winding and a secondary winding. A switch is connected to the secondary winding of the transformer. At least one capacitor is also connected to the secondary winding of the transformer with the switch.

Abstract: A frequency multiplier is provided that includes a switching component having a plurality of differential pairs of transistors. The frequency multiplier further includes a gain stage. A common mode feedback generated by the switching component is also provided to the gain stage.

Abstract: A double pole single throw (DPST) switch circuit including a first circuit portion corresponding to a first input port, a second circuit portion corresponding to a second input port, and an output port, wherein each of the first and second circuit portions include at least one first transistor providing a portion of an isolation channel, at least one second transistor providing a portion of a transmit channel, and at least one third transistor for providing a control bias for selecting either the transmit channel or the isolation channel.

Abstract: A voltage controlled oscillator (VCO) is provided that includes an output buffer having a first buffer stage including a first transistor and a second buffer stage including a second transistor. The first and second transistors are connected in a cascaded emitter follower buffer arrangement.

Abstract: The invention is a method and circuit for generating a pulsed periodic signal comprising a sub-harmonic mixer and a control circuit adapted to cause the output signal of the sub-harmonic mixer to be pulsed.

Abstract: A method and apparatus for generating short electronic pulses using a modified differential trigger that is partly an analogue sinusoidal voltage and partly a selectable, DC voltage. The differential trigger is applied to a differential base band pulse generator having a NAND gate and AND gate. The trigger is applied to both NAND inputs and to one AND input. The NAND output is applied the other AND input. Such a circuit is an OFF state for all input states. However, as the input switches state, the NAND gate delay causes the AND gate to be ON briefly, generating a short pulse. The timing of this pulse can be controlled by varying the constant DC voltage. By using fast switching SiGe CML gates, short pulses with a controllable time off-set can be generated that are suitable for use in automotive radar applications, using only sub-GHz clocks.

Abstract: A receiver circuit including a differential amplifier and at least one common mode feedback circuit coupled to the differential amplifier for providing a control current to the differential amplifier for regulating a common mode voltage of the differential amplifier. The receiver circuit provides integration and sampling on an input signal, and may be used as a portion of a sensor circuit.

Abstract: A receiver circuit including an oscillator, a mixer coupled to the oscillator, a switch coupled to an output of the mixer, and an envelope detector coupled to the oscillator, such that the envelope detector generates a timing signal for actuating the switch based on the envelope of a signal produced by the oscillator. In one exemplary embodiment, the receiver circuit may be used as part of a radar based sensor system.